EM78452WM datasheet(13/54 Pages) EMC

13 / 54 page

EM78452

8-Bit Microcontroller

Product Specification (V1.0) 10.18.2007

• 9

(This specification is subject to change without further notice)

5.1.11 RD (SPIC: SPI Control Register)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0D

SPIC/RD

CES

SPIE

SRO

SSE

SDOC SBRS2

SBRS1 SBRS0

Bit 7 (CES): Clock Edge Select bit

0 : Data shifts out on a rising edge, and shifts in on a falling edge. Data is

on hold during low-level.

1 : Data shifts out on a falling edge, and shifts in on a rising edge. Data is

on hold during high-level.

Bit 6 (SPIE): SPI Enable bit

0 : Disable SPI mode

1 : Enable SPI mode

Bit 5 (SRO): SPI Read Overflow bit

0 = No overflow

1 = A new data is received while the previous data is still being held in the

SPIB register. In this situation, the data in the SPIS register will be

destroyed. To avoid setting this bit, users are required to read the

SPIRB register although only the transmission is implemented.

Note that this can only occur in slave mode.

Bit 4 (SSE): SPI Shift Enable bit

0 = Reset as soon as shifting is completed, and the next byte is ready to

be shifted.

1 = Start to shift, and keep at “1” while the current byte is still being

transmitted.

It should be noted that this bit will be reset to 0 at every 1-byte

transmission by the hardware.

Bit 3 (SDOC): SDO output status control bit:

0 : After the Serial data output, the SDO remains high.

1 : After the Serial data output, the SDO remains low.

Bit 2~Bit 0 (SBRS): SPI Baud Rate Select bits

Refer to the SPI baud rate table illustration under the section “SPI” on the

subsequent pages.

5.1.12 RE (TMR1: Timer 1 Register)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0X0E

TMR1/RE TMR17 TMR16 TMR15 TMR14 TMR13 TMR12 TMR11 TMR10

TMR17~TMR10 are the set of bits of Timer 1 register and such are incremented until

the value matches PWP and then it resets to 0.

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