TA8483CP_06 datasheet(4/22 Pages) TOSHIBA

4 / 22 page

TA8483CP

2006-3-2

Functional Description

1. Output section (OUT

−U, OUT−V, OUT−W)

• The configuration of the output stage is shown in

the chart to the right.

• The PWM operation takes off−on control of the

upper side transistor.

• Be sure to set the schottky barrier diode outside,

because the current flows to the lower

−side diode

when PWM is off.

2. Input circuit (IN

−U, IN−V, IN−W)

• The three−phase input receivs three−state

impedance (high. low, high impedance) from the

controller side.

3. Overheat protection circuit

• When junction temperature Tj is Tj≥TSD (on)

(overheat protection operation temperature)

when TSD

−SEL = "low", the entire output

maintains an off state.

To cancel this state,

(1) Reapply the supply voltage.

(2) Apply "

" signal to the TSD

−SEL pin.

• When TSD−SEL = "high", an automatic return

mode takes place.

4. Excess current detection circuit (VISD, ISD)

• The voltage in current detection resistor RF

outside VI pin is input to the VISD pin.

• When VISD voltage rises above internal reference

voltage VRF (≃ 0.5V), excess current detection

circuit ISD becomes "high".

OUT−U

OUT−V

OUT−W

10 VCC

10kΩ

50kΩ

11, 12, 13

< Output circuit >

< Input circuit >

Internal logic

power supply

(≃ 6.7V)

Lower side

PwTr control

Circuit

Upper side

PwTr control

circuit

VISD

ISD

< Excess current detection circuit >

Internal logic

power supply

(≃ 6.7V)

−

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