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T6LE2 датащи(PDF) 4 Page - Toshiba Semiconductor |
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T6LE2 датащи(HTML) 4 Page - Toshiba Semiconductor |
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4 / 12 page ![]() T6LE2 2006-09-20 4 Pin Function Pin Name I/O Function DI/O DO/I I/O Vertical shift clock, output enable input / output select pin These pins are used to input and output shift data. These pins are switched between input and output by setting the U/D pin as shown below. U/D DI/O DO/I H Input Output L Output Input • When set for input This pin is used to feed data into the shift registers at the first stage of the LCD driver. The data is latched into the shift registers at the rising edge of CPVL/R. • When set for output When two or more T6LE2 are cascaded, this pin outputs the data to be fed into the next stage. This data changes state synchronously with the falling edge of CPVL/R. U/DL U/DR I/O Transfer direction select / vertical shift clock, output enable input / output select pin This pin specifies the direction in which data is transferred through the shift registers. The shift register data is shifted synchronously with the rising edge of CPV as follows: When U/D is high, data is shifted in the direction U/D = “H”: G1 → G2 → G3 → G4 → ··· → G300 When U / D is low, the direction is reversed to give U/D = “L”: G300 → G299 → G298 → G297 → ··· → G1 This pin is used to perform input / output settings for CPVL, CPVR, OE L, OE R. U/D Input Output CPVR CPVL L OE R OE L CPVL CPVR H OE L OE R The voltage applied to this pin must be a DC-level voltage that is either high (VDD) or low (VSS). CPVL CPVR I/O Vertical shift clock • When set for input: This is the shift clock for the shift registers. Data is shifted through the shift registers synchronously with the rising edge of CPVL/R. • When set for output: The signal input to CPVL/R is output to CPVR/L asynchronous to other signals. These pins are switched between input and output by setting the U/D pin as below. U/D CPVL CPVR H Input Output L Output Input OE L OE R I/O Output enable pin When set for input: These signals control the data appearing at the LCD panel drive pins (G1 through G300). OE L/R doesn’t synchronize with the CPVL/R. When OE L/R is low : outputs shift data and data contents. When OE L/R is high : controls the LCD panel drive output to VEE level. When set for output: The signal input to OE L/R is output to OE R/L. These pins are switched between input and output by setting the U/D pin as below. U/D OE L OE R H Input Output L Output Input |
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