IL715/IL716/IL717

8

NVE Corporation

11409 Valley View Road, Eden Prairie, MN 55344-3617

(952) 829-9217

www.nve.com

YouTube.com/NveCorporation

iso-apps@nve.com

Insulation Specifications

Parameter

Symbol

Min.

Typ.

Max.

Units

Test Conditions

Creepage Distance

(external)

QSOP

0.15" SOIC

0.3" SOIC

4.03

4.03

8.03

8.3

mm

Per IEC 60601

Total Barrier Thickness (internal)

0.012

0.016

mm

Leakage Current(5)

0.2

µA

240 VRMS, 60 Hz

Barrier Resistance(5)

>1014

Ω

500 V

Barrier Capacitance(5)

4

pF

f = 1 MHz

Comparative

Tracking Index

QSOP

0.15" SOIC

0.3" SOIC

CTI

≥

175

≥

175

≥

600

VRMS

Per IEC 60112

High Voltage Endurance

(Maximum Barrier Voltage

for Indefinite Life)

AC

DC

VIO

1000

1500

VRMS

VDC

At maximum

operating temperature

Surge Immunity (“V” Versions)

VIOSM

12.8

kVPK

Per IEC 61000-4-5

Barrier Life

44000

Years

100°C, 1000 VRMS,

60% CL activation

energy

Thermal Characteristics

Parameter

Symbol

Min.

Typ.

Max.

Units

Test Conditions

Junction–Ambient

Thermal Resistance

QSOP

0.15" SOIC16

0.3" SOIC16

θ

JA

100

82

67

°C/W

Double-sided PCB in

free air

Junction–Case (Top)

Thermal Resistance

QSOP

0.15" SOIC16

0.3" SOIC16

θ

JC

9

8

12

Junction–Ambient

Thermal Resistance

0.3" SOIC

θ

JA

46

2s2p PCB in free air

per JESD51

Junction–Case (Top)

Thermal Resistance

θ

JC

9

Power Dissipation

QSOP

0.15" SOIC16

0.3" SOIC16

PD

675

675

1500

mW

Notes (apply to both 3.3 V and 5 V specifications):

1.

Absolute maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not

guarantee performance.

2.

PWD is defined as |tPHL − tPLH|. %PWD is equal to PWD divided by pulse width.

3.

tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH between devices at 25 °C.

4.

CMH and CML are the maximum common mode voltage slew rates that can be applied with the outputs remaining stable and within VOL and

VOH specifications.

5.

Device is considered a two terminal device: pins 1–8 shorted and pins 9–16 shorted.

6.

Dynamic power consumption is calculated per channel.

7.

Minimum pulse width is the minimum value at which specified PWD is guaranteed.

8.

The relevant test and measurement methods are given in the Electromagnetic Compatibility section on p. 10.

9.

External magnetic field immunity is improved by this factor if the field direction is “end-to-end” rather than to “pin-to-pin” (see diagram on p. 10).

10. 66,535-bit pseudo-random binary signal (PRBS) NRZ bit pattern with no more than five consecutive 1s or 0s; 800 ps transition time.