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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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KSZ9567R датащи(PDF) 76 Page - Microchip Technology |
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KSZ9567R датащи(HTML) 76 Page - Microchip Technology |
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76 / 233 page  KSZ9567R DS00002329E-page 76 2022 Microchip Technology Inc. and its subsidiaries 5.1.2.3 In-Band Management (IBA) Control Register This register controls the In-Band Access (IBA) feature. 4:2 SYNCLKO Source 000 = From crystal / clock input at XI pin 001 = From port 1 recovered clock 010 = From port 2 recovered clock 011 = From port 3 recovered clock 100 = From port 4 recovered clock 101 = From port 5 recovered clock 110 – 111 = Reserved R/W 000b 1 SYNCLKO Output Pin Enable 0 = Disabled 1 = Enabled R/W 1b 0 SYNCLKO Frequency 0 = 25 MHz 1 = 125 MHz R/W 0b Address: 0x0104 - 0x0107 Size: 32 bits Bits Description Type Default 31 IBA Enable The initial value is strapped in from the RX_DV7/CRS_DV7/RX_CTL7 pin. 0 = Disabled 1 = Enabled Note: If using I2C, do not enable IBA. R/W Note 5-1 30 IBA Destination MAC Address Match Enable Set this bit to enable checking of the destination MAC address in received IBA frames against the switch MAC address in the Switch MAC Address 0 Register through Switch MAC Address 5 Register. Non-matching frames are discarded. When not enabled, the MAC address is not checked. R/W 0b 29 IBA Reset Set this bit to initialize the IBA state machine. This bit is self-clearing. R/W SC 0b 28:24 RESERVED RO 0x00 23:22 Priority Queue for IBA response Specifies the transmit priority queue for the IBA response frame. Typically this value is not changed. R/W 01b 21:19 RESERVED RO 00_0b Bits Description Type Default |
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