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ATSHA204A датащи(PDF) 30 Page - Microchip Technology |
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ATSHA204A датащи(HTML) 30 Page - Microchip Technology |
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30 / 93 page ![]() Figure 6-3. NACK and ACK Conditions on I2C Interface Data Output by Receiver SCL from Master Data Output by Transmitter Clock Pulse for Acknowledgment Start Condition S Not Acknowledge Acknowledge 12 8 9 Multiple ATSHA204A devices can share the same I2C interface if the I2C_Address byte is programmed differently for each device on the bus. Because six of the bits of the device address are programmable, the ATSHA204A can also share the I2C interface with any standard I2C device, including any serial EEPROM. Bit 3 (also known as TTL Enable) must be programmed according to the input thresholds desired and it is fixed in a particular application. 6.2 I2C Transmission to the ATSHA204A Device The transmission of data from the system to the ATSHA204A is summarized in the figure below. The order of transmission is as follows: 1. Start Condition 2. Device Address Byte 3. Word Address Byte 4. Optional Data Bytes (1 through N) 5. Stop Condition Figure 6-4. Normal I2C Transmission to an ATSHA204A 1-7 8 9 1-7 8 9 1-7 8 9 1-7 8 9 1-7 8 9 SCL SDA S P R/W ACK1 ACK1 ACK1 Word Address Data 1 ACK1 Data 2 Start Condition Stop Condition Device Address ACK1 Data N Note: SDA is driven low by the ATSHA204A during the ACK periods The following table labels the bytes of the I/O transaction. The I2C name column provides the names of the bytes as they are described in the AT24C16 Datasheet. Table 6-1. I2C Transmission to the ATSHA204A ATSHA204A I2C Name Direction Description Device Address Device Address To Slave This byte selects a particular device on the I2C interface. The ATSHA204A is selected if bits 1 through 7 of this byte match bits 1 thru ATSHA204A I2C Interface © 2018 Microchip Technology Inc. DS40002025A-page 30 |
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