TMP86FS49AIUG datasheet(200/296 Pages) TOSHIBA

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Page 184

15. Synchronous Serial Interface (SIO2)

15.3 Function

TMP86FS49AIUG

(2)

During the transmit operation

When data is written to SIO2TDB, SIO2SR<TXF> is cleared to “0”.

In internal clock operation, in case a next transmit data is not written to SIO2TDB, the serial clock

stops to “H” level by an automatic-wait function when all of the bit set in the SIO2TDB has been

transmitted. Automatic-wait function is released by writing a transmit data to SIO2TDB. Then, trans-

mit operation is restarted after maximum 1-cycle of serial clock.

When the next data is written to the SIO2TDB before termination of previous 8-bit data with

SIO2SR<TXF> “1”, the next data is continuously transferred after transmission of previous data.

In external clock operation, after SIO2SR<TXF> is set to “1”, the transmit data must be written to

SIO2TDB before the shift operation of the next data begins.

If the transmit data is not written to SIO2TDB, transmit error occurs immediately after shift opera-

tion is started. Then, INTSIO2 interrupt request is generated after SIO2SR<TXERR> is set to “1”.

(3)

Stopping the transmit operation

There are two ways for stopping transmits operation.

• The way of clearing SIO2CR<SIOS>.

When SIO2CR<SIOS> is cleared to “0”, transmit operation is stopped after all transfer of the

data is finished. When transmit operation is finished, SIO2SR<SIOF> is cleared to “0” and

SO2 pin is kept in high level.

In external clock operation, SIO2CR<SIOS> must be cleared to “0” before SIO2SR<SEF> is

set to “1” by beginning next transfer.

• The way of setting SIO2CR<SIOINH>.

Transmit operation is stopped immediately after SIO2CR<SIOINH> is set to “1”. In this

case, SIO2CR<SIOS>, SIO2SR register, SIO2RDB register and SIO2TDB register are ini-

tialized.

Figure 15-6 Example of Internal Clock and MSB Transmit Mode

A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1

C6 C5 C4 C3 C2 C1 C0

Automatic wait

Start shift

operation

Start shift

operation

Start shift

operation

Writing transmit

data B

Writing transmit

data A

Writing transmit

data C

Clearing SIOS

SIO2CR<SIOS>

SIO2SR<SIOF>

SIO2SR<SEF>

SCK2

pin output

SO2 pin

SIO2SR<TXF>

SIO2TDB

INTSIO2

interrupt

request

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