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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP86FS49AIUG датащи(PDF) 197 Page - Toshiba Semiconductor |
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TMP86FS49AIUG датащи(HTML) 197 Page - Toshiba Semiconductor |
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197 / 296 page  Page 181 TMP86FS49AIUG (2) External clock When an external clock is selected by setting SIO2CR<SCK> to “111B”, the clock via the SCK2 pin from an external source is used as the serial clock. To ensure shift operation, the serial clock pulse width must be 4/fc or more for both “H” and “L” levels. Figure 15-3 External Clock 15.3.1.2 Shift edge The leading edge is used to transmit data, and the trailing edge is used to receive data. (1) Leading edge shift Data is shifted on the leading edge of the serial clock (falling edge of the SCK2 pin input/output). (2) Trailing edge shift Data is shifted on the trailing edge of the serial clock (rising edge of the SCK2 pin input/output). Figure 15-4 Shift Edge tSCKL tSCKH tSCKL, tSCKH > 4/fc SCK2 pin 7******* ******** Bit7 Shift out ***01234 **012345 *0123456 Bit5 Bit6 Bit5 Bit6 Bit7 67****** 567***** (a) Leading edge shift (Example of MSB transfer) (b) Trailing edge shift (Example of MSB transfer) 01234567 ****0123 *****012 ******01 *******0 ******** Bit4 4567**** 34567*** 234567** 1234567* 01234567 Bit4 Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 SIO2CR<SIOS> SCK2 pin Shift register SO2 pin Shift register SCK2 pin SI2 pin SIO2CR<SIOS> |
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