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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP86FS49AIUG датащи(PDF) 161 Page - Toshiba Semiconductor |
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TMP86FS49AIUG датащи(HTML) 161 Page - Toshiba Semiconductor |
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161 / 296 page  Page 145 TMP86FS49AIUG 12.9 Status Flag 12.9.1 Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UART1SR<PERR> is set to “1”. The UART1SR<PERR> is cleared to “0” when the RD1BUF is read after reading the UART1SR. Figure 12-5 Generation of Parity Error 12.9.2 Framing Error When “0” is sampled as the stop bit in the receive data, framing error flag UART1SR<FERR> is set to “1”. The UART1SR<FERR> is cleared to “0” when the RD1BUF is read after reading the UART1SR. Figure 12-6 Generation of Framing Error 12.9.3 Overrun Error When all bits in the next data are received while unread data are still in RD1BUF, overrun error flag UART1SR<OERR> is set to “1”. In this case, the receive data is discarded; data in RD1BUF are not affected. The UART1SR<OERR> is cleared to “0” when the RD1BUF is read after reading the UART1SR. Parity Stop Shift register pxxxx0* 1pxxxx0 xxxx0** RXD1 pin UART1SR<PERR> INTRXD1 interrupt After reading UART1SR then RD1BUF clears PERR. Final bit Stop Shift register xxxx0* 0xxxx0 xxx0** RXD1 pin UART1SR<FERR> INTRXD1 interrupt After reading UART1SR then RD1BUF clears FERR. |
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