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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP86CS25AFG датащи(PDF) 71 Page - Toshiba Semiconductor |
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TMP86CS25AFG датащи(HTML) 71 Page - Toshiba Semiconductor |
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71 / 194 page  Page 61 TMP86CS25AFG 6. Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the CPU to a system recovery routine. The watchdog timer signal for detecting malfunctions can be programmed only once as “reset request” or “inter- rupt request”. Upon the reset release, this signal is initialized to “reset request”. When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic inter- rupt. Note: Care must be taken in system design since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 6.1 Watchdog Timer Configuration Figure 6-1 Watchdog Timer Configuration 0034H Overflow WDT output Internal reset Binary counters WDTOUT Writing clear code Writing disable code WDTEN WDTT 2 0035H Watchdog timer control registers WDTCR1 WDTCR2 INTWDT interrupt request Interrupt request Reset request Reset release Clock Clear 1 2 Controller Q SR S R Q fc/223 or fs/215 fc/221 or fs/213 fc/219 or fs/211 fc/217 or fs/29 |
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