should be isolated from "clean" circuits where possible, and

grounded through a separate path. At MHz frequencies,

ground planes begin to look inductive and RFI/EMI can cause

ground bounce across the ground plane. In multi-layer PC

Board applications, care should be taken in layout so that

noisy power and ground planes do not radiate directly into

adjacent layers which carry analog power and ground.

OUTPUT NOISE

Noise is specified in two ways-

Spot Noise or Output noise density is the RMS sum of all

noise sources, measured at the regulator output, at a specific

frequency (measured with a 1Hz bandwidth). This type of

noise is usually plotted on a curve as a function of frequency.

Total output noise voltage or Broadband noise is the RMS

sum of spot noise over a specified bandwidth, usually several

decades of frequencies. Attention should be paid to the units

of measurement.

Spot noise is measured in units µV/

output noise is measured in µV(rms). The primary source of

noise in low-dropout regulators is the internal reference. In

CMOS regulators, noise has a low frequency component and

a high frequency component, which depend strongly on the

silicon area and quiescent current.

Noise can generally be reduced in two ways: increase the

transistor area or increase the reference current. However,

enlarging the transisitors will increase die size, and increasing

the reference current means higher total supply current

(ground pin current).

SHORT-CIRCUIT PROTECTION

The LP38501/3-ADJ contains internal current limiting which

will reduce output current to a safe value if the output is over-

loaded or shorted. Depending upon the value of V

limiting may also become active as the average power dissi-

pated causes the die temperature to increase to the limit value

(about 170°C). The hysteresis of the thermal shutdown cir-

cuitry can result in a “cyclic” behavior on the output as the die

temperature heats and cools.

ENABLE OPERATION (LP38501-ADJ Only)

The Enable pin (EN) must be actively terminated by either a

10 k

Ω pull-up resistor to V

high and low (such as a CMOS rail to rail comparator). If active

drive is used, the pull-up resistor is not required. This pin must

be tied to V

DROPOUT VOLTAGE

The dropout voltage of a regulator is defined as the input-to-

output differential required by the regulator to keep the output

voltage within 2% of the nominal value. For CMOS LDOs, the

dropout voltage is the product of the load current and the

R

Since the output voltage is beginning to “drop out” of regula-

tion when it drops by 2%, electrical performance of the device

will be reduced compared to the values listed in the Electrical

Characteristics table for some parameters (line and load reg-

ulation and PSRR would be affected).

REVERSE CURRENT PATH

The internal MOSFET pass element in the LP38501/3-ADJ

has an inherent parasitic diode. During normal operation, the

input voltage is higher than the output voltage and the para-

sitic diode is reverse biased. However, if the output is pulled

above the input in an application, then current flows from the

output to the input as the parasitic diode gets forward biased.

The output can be pulled above the input as long as the cur-

rent in the parasitic diode is limited to 200 mA continuous and

1A peak. The regulator output pin should not be taken below

ground potential. If the LP38501/3-ADJ is used in a dual-sup-

ply system where the regulator load is returned to a negative

supply, the output must be diode-clamped to ground.

POWER DISSIPATION/HEATSINKING

The maximum power dissipation (P

ADJ is limited by the maximum junction temperature of

125°C, along with the maximum ambient temperature (T

A

the package. Under all possible conditions, the junction tem-

perature (T

ating Ratings. The total power dissipation of the device is

given by:

P

(1)

where I

(specified under Electrical Characteristics).

The maximum allowable junction temperature rise (

ΔT

pends on the maximum expected ambient temperature

(T

tion temperature (T

ΔT

(2)

The maximum allowable value for junction to ambient Ther-

mal Resistance,

θ

θ

(3)

The LP38501/3-ADJ is available in the TO-263 package. The

thermal resistance depends on the amount of copper area

allocated to heat transfer.

HEATSINKING TO-263, TO-263 THIN PACKAGES

The TO-263 package and TO-263 THIN package use the

copper plane on the PCB as a heatsink. The DAP of the pack-

age is soldered to the copper plane for heat sinking. Figure

12 shows a typical curve for the

θ

for different copper area sizes (the thermal performance of

both the TO-263 and TO-263 THIN are the same). The tests

were done using a PCB with 1 ounce copper on top side only

which were square in shape.

13

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