AD9913

Rev. 0 | Page 27 of 32

REGISTER BIT DESCRIPTIONS

The serial I/O port registers span an address range of 0 to 16

(0x00 to 0x10 in hexadecimal notation). This represents a total

of 17 registers. However, one of these registers (0x05) is unused,

yielding a total of 16 available registers.

The registers are not of uniform depth; each contains the

number of bytes necessary for its particular function.

Additionally, the registers are assigned names according to their

functionality. In some cases, a register is given a mnemonic

descriptor. For example, the register at Serial Address 0x00 is

named Control Function Register 1 and is assigned the

mnemonic CFR1.

The following section provides a detailed description of each bit

in the AD9913 register map. For cases in which a group of bits

serve a specific function, the entire group is considered as a

binary word and described in aggregate.

This section is organized in sequential order of the serial

addresses of the registers. Each subheading includes the register

name and optional register mnemonic (in parentheses). Also

given is the serial address in hexadecimal format and the

number of bytes assigned to the register.

Following each subheading is a table containing the individual

bit descriptions for that particular register. The location of the

bit(s) in the register are indicated by a single number or a pair

of numbers separated by a colon. A pair of numbers (A:B)

indicates a range of bits from the most significant (A) to the

least significant (B). For example, 5:2 implies Bit Position 5

down to Bit Position 2, inclusive, with Bit 0 identifying the LSB

of the register.

Unless otherwise stated, programmed bits are not transferred to

their internal destinations until the assertion of the I/O_UPDATE

pin or a profile change.

Control Function Register 1 (CFR1)

Address 0x00; 4 bytes are assigned to this register.

Table 10. Bit Description for CFR1

Bit(s)

Bit Name

Description

31:29

Open

Leave these bits at their default values.

This bit is ignored if linear sweep is disabled.

0 = the auxiliary accumulator is used for linear sweep generation.

28

Modulus Enable

1 = the auxiliary accumulator is used for programmable modulus.

27

Use Internal Profile

0 = profiles are controlled by profile pins; only valid in serial mode.

1 = profiles are controlled by CFR1 [22:20].

26

Match Pipeline Delays Active

0 = the latency across the auxiliary accumulator, the phase offset word, and phase

accumulator are matched.

1 = the latency across the auxiliary accumulator, the phase offset word, and phase

accumulator are not matched.

25:24

Open

Leave these bits at the default values.

0 = MSB first format is used.

23

LSB First

1 = LSB first format is used.

22:20

Internal Profile Control

details on how to program these registers during linear sweep, and refer to the Direct

Switch Mode section for details on how to program these registers in direct switch mode.

19

Sync Clock Disable

0 = the SYNC_CLK pin is active.

1 = the SYNC_CLK pin assumes a static Logic 0 state (disabled). In this state, the pin drive

logic is shut down, minimizing the noise generated by the digital circuitry.

18:17

Open

Leave these bits in their default values.

16

Direct Switch Mode Active

0 = direct switch mode is disabled.

1 = direct switch mode is enabled.

0 = normal operation of the auxiliary accumulator (default).

15

Clear Auxiliary Accumulator

1 = asynchronous, static reset of the auxiliary accumulator. The ramp accumulator remains

reset as long as this bit remains set. This bit is synchronized with either an I/O update or a

profile change and the next rising edge of SYNC_CLK.

0 = normal operation of the DDS phase accumulator (default).

14

Clear Phase Accumulator

1 = asynchronous, static reset of the DDS phase accumulator.