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formation about the data classes are passed

as result to appropriate internal module.

Shifter –

performs mantissa shifting during

normalization, denormalization operations.

Information about shifted-out bits are stored

for rounding process.

Control Unit –

manages execution of all

instructions and internal operation required to

execute particular function.

Interface –

makes interface between exter-

nal device and DFPMU-DP internal 32-bit

modules. It contains data, control and status

registers. It can be configured to work with 8-,

16- and 32-bit processors.

PERFORMANCE

The following table gives a survey about

the Core area and performance in the AL-

TERA® devices after Place & Route (all key

features have been included):

Device

Speed

grade

Logic Cells

CYCLONE

-6

7070

77 MHz

CYCLONE-II

-6

7080

68 MHz

STRATIX

-5

7070

82 MHz

STRATIX-II

-3

5290

109 MHz

Core performance in ALTERA® devices

DFPMU-DP floating point instructions per-

formance has been compared to standard C

library functions delivered with every com-

mercial C compiler. Each program was exe-

cuted in the same system environments.

Number of clock periods were measured be-

tween input data loading into work registers

and output result storing after operation.

The results are placed in table below. Im-

provement has been computed as number of:

(NIOS-II CLK) divided by (NIOS-II+DFPMU-

DP CLK), required to execute particular in-

struction.

IEEE-754 FP Instruction

Improvement

Addition

12.0

Subtraction

11.7

Multiplication

10.6

Division

15.0

Square Root

21.5

Sine

52.0

Cosine

60.8

Tangent

97.9

Arcs Tangent

78.7

Average speed improvement:

38.3

More details are available in core docu-

mentation.

The following table gives a survey about

the 32-bit NIOS-II+DFPMU-DP performance

compared to 32-bit NIOS-II.

Device

Improvement

NIOS-II

1.0

NIOS-II+DFPMU (arithmetic)

14.1

NIOS-II+DFPMU (trigonometric)

72.4

NIOS-II+DFPMU (overall)

38.8