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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMPR4956C датащи(PDF) 58 Page - Toshiba Semiconductor |
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TMPR4956C датащи(HTML) 58 Page - Toshiba Semiconductor |
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58 / 286 page  Chapter 2 Features 2-10 Table 2.2.8 Initialization Interface Signal Name Pin No. I/O Function Reset* R13 I Reset (with pull-up resistor). This signal should be asserted for soft reset. See section 9.2.3 SoftReset in detail. ColdReset* R14 I Cold reset This signal should be assert at power-on and for a cold reset. GBUSCLK starts operating synchronously with this signal. See section 9.2.2 ColdReset in detail. PLLReset* P2 I PLL reset input This signal should be asserted for initialization of the on-chip PLL, for example, when the system power is turned on. See section 9.2.1 Power-On Reset in detail. MODE43* B15 I SysAD bus protocol selection The high or low level of this input signal at power-on or cold reset selects the SysAD bus protocol. 0: R4300 type protocol 1: R5000 type protocol BSIZE64* R4 I SysAD bus width selection The high or low level of this input signal selects the SysAD bus address and data width 0: 64-bit bus width 1: 32-bit bus width (TX4955 mode or R4300 type protocol) BufSel B1 I Output Buffer Select Select the output buffer type of data bus and control signals. BufSel Buffer output rate 0 100 % (16-mA buffer type) 1 50 % (8-mA buffer type) Please not change the value after power-on. |
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