SM5816AF

SEIKO NPC CORPORATION —21

RAM coefficient write mode (bit 1 = “H”)

In RAM coefficient write mode, the bit represent a RAM write address and coefficient write data, with the first

40 bits of data being valid.

Note. Writing RAM coefficients always takes precedence. As a result, coefficient writing while a RAM coefficient is selected, will mean the coefficients are

read incorrectly, generating an output noise. To prevent this problem, the outputs should be muted when writing RAM coefficients or a ROM coeffi-

cient should be temporarily selected.

Table 2. Flag function table

Bit

Flag name

Function

Value or state

1

MODE

RAM coefficient write mode

Tied "H"

2

(Reserved)

Reserved flag

Tied "L"

3

(Reserved)

Reserved flag

Tied "L"

4

COEF28

Coefficient data (MSB)

Coefficient data must conform with the following conditions.

* Coefficient word length = 29 bits (

± 1.0)

* Coefficient sum total not to exceed 0.5

(18000000)h to (07FFFFFF)h

* Depending on the coefficient, the result may pass the overflow limit.

* RAM initial state is indeterminate, thus address-field data must be written before use.

5

COEF27

Coefficient data

6

COEF26

Coefficient data

7

COEF25

Coefficient data

8

COEF24

Coefficient data

9

COEF23

Coefficient data

10

COEF22

Coefficient data

11

COEF21

Coefficient data

12

COEF20

Coefficient data

13

COEF19

Coefficient data

14

COEF18

Coefficient data

15

COEF17

Coefficient data

16

COEF16

Coefficient data

17

COEF15

Coefficient data

18

COEF14

Coefficient data

19

COEF13

Coefficient data

20

COEF12

Coefficient data

21

COEF11

Coefficient data

22

COEF10

Coefficient data

23

COEF9

Coefficient data

24

COEF8

Coefficient data

25

COEF7

Coefficient data

26

COEF6

Coefficient data

27

COEF5

Coefficient data

28

COEF4

Coefficient data

29

COEF3

Coefficient data

30

COEF2

Coefficient data

31

COEF1

Coefficient data

32

COEF0

Coefficient data (LSB)

33

RA7

RAM write address (MSB)

Coefficient address should be assigned as follows.

* Even-order symmetrical coefficients restriction means that only half need be written

from the edges to the center.

* For 2fs, half 480th-order implies to address 240.

RA = (00)h is the edge, RA = (EF)h is the center.

* For 8fs, half 240th-order implies to address 120.

RA = (00)h, the edge, to RA = (3B)h are the first 60 addresses

RA = (80)h to RA = (BB)h are the last 60 addresses.

34

RA6

RAM write address

35

RA5

RAM write address

36

RA4

RAM write address

37

RA3

RAM write address

38

RA2

RAM write address

39

RA1

RAM write address

40

RA0

RAM write address (LSB)