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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IIS2DULPX датащи(PDF) 39 Page - STMicroelectronics |
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IIS2DULPX датащи(HTML) 39 Page - STMicroelectronics |
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39 / 106 page  8 Register description 8.1 EXT_CLK_CFG (08h) R/W Table 20. EXT_CLK_CFG register EXT_CLK_EN 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 1. This bit must be set to 0 for the correct operation of the device. Table 21. EXT_CLK_CFG register description EXT_CLK_EN If this bit is set to 1, the external clock, forced through the RES/EXT_CLK pin, replaces the internal oscillator. Default value: 0 Supported frequency for the external clock is: 102.4 kHz ± 5%, supported duty cycle 50% ± 10% 8.2 PIN_CTRL (0Ch) R/W Table 22. Table 20. PIN_CTRL register SDO_PU_EN SDA_PU_EN PD_DIS_INT2 PD_DIS_INT1 H_LACTIVE CS_PU_DIS PP_OD SIM Table 23. PIN_CTRL register description SDO_PU_EN If 1, enables the internal pull-up of the SDO/TA0 pin. SDA_PU_EN If 1, enables the internal pull-up of the SDA/SDI/SDO pin. PD_DIS_INT2 If 1, disables the internal pull-down of the INT2 pin. PD_DIS_INT1 If 1, disables the internal pull-down of the INT1 pin. H_LACTIVE Interrupt active level (0: interrupts active-high (default); 1: Interrupts active-low) CS_PU_DIS If 1, disables the internal pull-up of the CS pin. PP_OD Push-pull/open-drain mode for INT pins (0: INT pins in push-pull mode (default); 1: INT pins in open-drain mode) SIM SPI 3 or 4-wire mode (0: 4-wire SPI (default); 1: 3-wire SPI) IIS2DULPX Register description DS14580 - Rev 1 page 39/106 |
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