| поискавой системы для электроныых деталей |
|
GIGA090 датащи(PDF) 2 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
GIGA090 датащи(HTML) 2 Page - STMicroelectronics |
|
2 / 4 page ![]() GIGA090 2/4 Functional Description GIGA090 IP supports three different Ethernet protocols: 10BASE-T, 100BASE-TX and 1000BASE-T, and can be configured to either Full Duplex or Half Duplex mode for each protocol. GIGA090 IP integrates all encoding, decoding, data recovery, clock recovery, scrambling, descrambling, digital adaptive equalization, echo cancellation, crosstalk cancellation, ADC, DAC, line transmission, link integrity, MAC and management interface functions that are required for 10Mb/s, 100Mb/s, and 1000Mb/s data transmission. It can be manually configured, be programmed or automatically determine its operating mode depending on the capabilities of the tranceiver on the opposite end of the link and the capabilities of the cable. The GIGA090 IP consists of 8 functional blocks: ● Auto-Negotiation block, which is responsible for advertising the chip’s capabilities and establishing the link. ● Management Register block, which contains all the configuration registers ● Management Data Interface ● Physical Coding Sublayer block, which contains the 1000/100/10 Base T sub-blocks ● Mac Interface. ● DPMA: Digital Physical Media Attachment, which consists of 1000/100/10 Base T sub- blocks: ● Clock Distribution and Reset circuitry. ● Status LED managment block. Figure 1. GIGA090 block diagram Side-Stream Scrambler Trellis Encoder 4D-PAM5 Encoder Pulse Shaping DAC Filter and Driver 4B/5B Encoder Scrambler Parallel to Serial NRZ to NRZI MLT3 Encoder Manchester Encoder Link Pulse Generator 10 TX Filter Descrambler and Alignment Viterbi & 4DPAM5 Decoders Echo Canceller Xtalk Canceller Adaptive Equalizer Hybrid Clk Recovery Baseline Wander ADC 4B/5B Decoder Descrambler NRZI to NRZ and Serial to Parallel MTL3 Decoder Manchester Decoder Link Pulse Detector 10 TX Filter Clock Recovery SMART Squelch Configuration LED interface Clock Generator JTAG Mgmt Interface Register Set Auto-Negotiation Analog PMD Mac Interface TPAP/N TPBP/N TPCP/N TPDP/N TX-EN TX-ER TXD[7:0] GTX-CLK TX_CLK COL CRS RX-DV RX-ER RXD[7:0] RX-CLK RBC0 RBC1 MAC Interface |
|
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |