DS1WM datasheet(5/20 Pages) MAXIM

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DS1WM

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For each bit position n (values from 0 to 63) the 1-Wire Master will generate three time slots on the 1-

Wire bus. These are referenced as:

for the first time slot (read data)

for the second time slot (read data) and

for the third time slot (write data).

The 1-Wire Master determines the type of time slot b2 (write 1 or write 0) as follows:

= rn if conflict (as chosen by the host)

= b0 if no conflict (there is no alternative)

= 1 if error (there is no response)

The response bytes that will be in the data register for the CPU to read during a complete pass through a

Search ROM function using the Search Accelerator consists of 16 bytes as follows:

first byte

r’3

r’2

r’1

r’0

et cetera

th byte

r’63

d63

r’62

d62

r’61

d61

r’60

d60

As before, the index designates the position of the bit in the ROM ID of a 1-Wire device. The character

“d” marks the discrepancy flag in that particular bit position. The discrepancy flag will be 1 if there is a

conflict or no response in that particular bit position and 0 otherwise. The character “r’” marks the

actually chosen path at that particular bit position. The chosen path is identical to b2 for the particular bit

position of the ROM ID.

To perform a Search ROM sequence one starts with all bits rn being 0s. In case of a bus error, all

subsequent response bits r’n are 1’s until the Search Accelerator is deactivated by writing 0 to bit 1 of the

Command register. Thus, if r’63 and d63 are both 1, an error has occurred during the search procedure and

the last sequence has to be repeated. Otherwise r’n (n=0…63) is the ROM code of the device that has

been found and addressed. When the Search ROM process is complete the SRA bit should be cleared in

order to release the 1-Wire Master from Search ROM Accelerator Mode.

For the next Search ROM sequence one re-uses the previous set rn (n=0…63) but sets rm to 1 with “m”

being the index number of the highest discrepancy flag that is 1 and sets all ri to 0 with i > m. This

process is repeated until the highest discrepancy occurs in the same bit position for two consecutive

passes.

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