© 2005 Microchip Technology Inc.

DS80172C-page 1

PIC18F8720/8620/6720/6620

The PIC18F8720/8620/6720/6620 parts you have

received conform functionally to the Device Data Sheet

(DS39609B), except for the anomalies described

below.

All of the issues listed here will be addressed in future

revisions of the PIC18F8720/8620/6720/6620 silicon.

The

following

silicon

errata

apply

only

to

PIC18F8720/8620/6720/6620 devices with these

Device/Revision IDs:

1.

Module: Core (Program Memory Space)

Performing table read operations above the user

program

memory

space

(addresses

over

1FFFFFh) may yield erroneous results at the

extreme low end of the device’s rated temperature

range (-40°C).

This applies specifically to addresses above

1FFFFFh,

including

the

user

ID

locations

(200000h-200007h),

the

configuration

bytes

(300000h-30000Dh) and the device ID locations

(3FFFFEh and 3FFFFFh). User program memory

is unaffected.

Work around

Two possible work arounds are presented. Other

solutions may exist.

1. Do not perform table read operations on areas

above the user memory space at -40°C.

2. Insert NOP instructions (specifically, literal

FFFFh) around any table read instructions. The

suggested optimal number is 4 instructions

before and 8 instructions after each table read.

This may vary depending upon the particular

application and should be optimized by the user.

Date Codes that pertain to this issue:

All engineering and production devices.

2.

Module: External Memory Interface

(PIC18F8620 only)

In Extended Microcontroller mode, or Micro-

processor mode, the external memory interface is

inactive from 20000h to 2FFFFh. ALE and WRL

signals are inactive between 20000h and 2FFFFh.

Work around

Shift RAM space to 30000h and above, or as an

alternate solution, the PIC18F8720 device can be

used.

This issue will be resolved in a future version of

silicon.

Date Codes that pertain to this issue:

All engineering and production devices.

3.

Module: I/O Ports (Parallel Slave Port)

While operating in Parallel Slave Port mode, the

OBF bit (PSPCON<6>) is supposed to be set

when a byte is written to either PORTD or LATD. It

has been noted that OBF may not be correctly set

when a byte is written to LATD. If the byte is written

to PORTD, then the OBF bit is set correctly.

Work around

To ensure the OBF bit is set correctly, write to

PORTD rather than LATD.

Date Codes that pertain to this issue:

All engineering and production devices.

4.

Module: A/D (External Voltage Reference)

and Comparator Voltage

Reference

selected for use with either the A/D or comparator

Work around

0V, enable the comparator voltage reference by

setting the CVREN bit in the CVRCON register.

comparator module.

Date Codes that pertain to this issue:

All engineering and production devices.

Part Number

Device ID

Revision ID

PIC18F6620

00 0110 011

00100

PIC18F6720

00 0110 001

00100

PIC18F8620

00 0110 010

00100

PIC18F8720

00 0110 000

00100

The Device IDs (DEVID1 and DEVID2) are located at

addresses

3FFFFEh:3FFFFFh

in

the

device’s

configuration space. They are shown in hexadecimal

in the format “DEVID2 DEVID1”.

PIC18F8720/8620/6720/6620 Rev. A4 Silicon/Data Sheet Errata