Direct Master or Direct Slave Operation

The PEX 8311 bridge provides master (Upstream traffic

generation) and slave (Downstream traffic acceptance)

capability. These transfers can occur simultaneously

with the DMA transfers and are given priority. For

master mode requests, the bridge services local bus

masters by generating Upstream traffic on the PCIe side.

There are two local bus address space maps to PCIe

(Direct Master mode): one to memory and one to I/O

with the bridge generating PCIe memory and I/O

transaction types. The bridge has independent large

depth Read and Write FIFOs. Read ahead and

programmable read pre-fetch counters enhance

performance. Register configuration is through the PCIe

port, Local Bus or through an optional EEPROM.

The PEX 8311 also supports direct slave requests where

the bridge services PCIe side Downstream traffic

initiators by mastering the Local Bus side. The bridge

has two general purpose address spaces and one

Expansion ROM space that could be used as a general

purpose direct slave space map to the Local Bus. Each

address space may be configured for 8-, 16-, or 32-bit

Local Bus data widths for flexible connectivity to Local

Bus devices. Independent Readand Write FIFOs of large

depth provide buffering. Performance is enhanced

through deferred writes, posted writes, read ahead, and

programmable read pre-fetch counters.

Hardware DMA Controls-EOT /Demand Mode

To optimize data transfers in many applications,

particularly communications, the PEX 8311 supports

hardware based control signals. When End of Transfer

(EOT#) is asserted, the bridge immediately terminates

the current transfer and indicates the number of bytes

transferred. Along with unlimited bursting capability,

EOT is useful in applications where the lengths of the

read packets are not known until the packets are read.

Additional hardware signaling control based DMA

transfers are available.

With Demand Mode each DMA channel has a pair of

hardware signals that are used to pause and resume the

current transfer. This allows a peripheral device such as

a line card with its own FIFO to control DMA transfers.

This mode can be used on many non-FIFO transfers as

well in a variety of end applications.

Advanced Performance Features

The PEX 8311 has a variety of added capabilities which

enhance throughput and flexibility for all transfer types:

DMA, Direct Master and Direct Slave. These include

zero wait state local bus bursts to 264 MB/s with

programmable burst lengths including unlimited

bursting, deep FIFO for maximum PCIe packet

generation, unaligned Local Bus transfers of any byte

length, on-the-fly Local Bus Endian conversion,

programmable Local Bus wait states, and Local Bus parity

checking. General purpose messaging for proprietary

message schemes include: eight 32-bit registers for

polled topologies and two 32-bit doorbell registers for

interrupt driven environments.

Fully Compliant Power Management

For applications that require power management, the

PEX 8311 device supports both link (L0, L0s, L1, L2/L3

Ready, and L3) and device (D0, D1, D2 and D3) power

management states, in compliance with the PCIe power

management specification. Full power management

event packets are generated and received and translated

to local bus signaling.

PLX I/O Accelerator Compatibility

The PEX 8311 is Register compatible with existing

PLX’s bus mastering Local Bus to PCI bridging

solutions (PLX PCI 9000 series). For many designs

migrating from PCI to PCIe, existing code utilizing these

I/O Accelerators can be used. As PCIe and PCI are

compatible, designs can quickly be extended to take

advantage of PCI Express’ bandwidth, system control,

and data integrity.

Internal Block Diagram

Figure 1 below shows an overview of the PEX 8311

Bridge. The device provides for full FIFO memory

buffers for each DMA channel and for Direct Master and

Direct Slave operation. A complete three layer PCIe

protocol interface with integrated SerDes provides

conversion from local bus data to/from PCI Express port

transfers. Modules for Hot Plug and power management

are included. Two serial EEPROM interfaces allow an

additional configuration option.

Applications

Suitable for Root Complex-centric as well as EndPoint

I/O applications, the PEX 8311 can be configured for a

wide variety of form factors and applications.

Figure 1. High-Speed Data Transfers

PCI Express

Interface

Generic

Local Bus

Interface

FIFOs

Hot Plug

PCI Express

Power

Management

Serial EEPROM

Serial EEPROM

PCI Express

Bus

Configuration

Registers

Serial

EEPROM

Interface

Local Bus

Configuration

Registers

Serial

EEPROM

Interface