DEVICES INCORPORATED

LF3321

Horizontal Digital Image Filter

Improved Performance

LOGIC Devices Incorporated

21

Feb 5, 2003 LDS.3321-A

Video Imaging Products

Vcc and GND

+3.3 V power supply. All pins must be connected.

CLK — Master Clock

The rising edge of CLK strobes all enabled registers.

to Filter B. Data is latched on the rising edge of clock.

In Single Filter Mode, RIN11-0 is the 12-bit reverse cascade input port. This port is connected to ROUT11-0

of another LF3321. In Dual Filter Mode, RIN11-0 can be the 12-bit input port to Filter B. Data is latched

on the rising edge of CLK.

CFA11-0 — Coefficient A Input

CFA11-0 is used to load data into the Filter A coefficient banks (banks 0 through 7) and the configuration/

control registers. Data present on CFA11-0 is latched into the Filter A LF InterfaceTM on the rising edge of

CLK when LDA is LOW (see the LF InterfaceTM section for a full discussion).

CAA7-0 — Coefficient Address A

CAA7-0 determines which row of data in coefficient banks 0 through 7 is fed to the multipliers. CAA7-0 is

latched into Coefficient Address Register A on the rising edge of CLK when CENA is LOW.

CFB11-0 — Coefficient B Input

CFB11-0 is used to load data into the Filter B coefficient banks (banks 8 through 15) and the configuration/

control registers. Data present on CFB11-0 is latched into the Filter B LF InterfaceTM on the rising edge of

CLK when LDB is LOW (see the LF InterfaceTM section for a full discussion).

CAB7-0 — Coefficient Address B

CAB7-0 determines which row of data in coefficient banks 8 through 15 is fed to the multipliers. CAB7-0 is

latched into Coefficient Address Register B on the rising edge of CLK when CENB is LOW.

Power

Signal Definitions

Clock

Inputs

Figure 23. Input Formats

11 10 9

2 1 0

(Sign)

11 10 9

2 1 0

(Sign)

Input Data

Coefficient Data

Figure 24. Accumulator Output Formats

31 30 29

2 1 0

(Sign)

31 30 29

2 1 0

(Sign)

Accumulator A Output

Accumulator B Output