The Embedded I/O Company

Technical Information

 Form Factor: Single-width 10 mm stacking height

FPGA Mezzanine Card (FMC) Mezzanine Module

conforming to ANSI/VITA 57.1

 Board size: 84 mm x 69 mm

 Air cooled Commercial Grade with Front Panel

 Regions 1, 2 and 3 populated

 High Pin Count (HPC) FMC Connector

 10 differential MGT interfaces are looped-back

 ADC with JTAG Interface to measure voltages

 Reconfigurable Spartan-II FPGA with Platform Flash

 40 MHz Clock

 68+48 FMC Bank A signals powered by VADJ

 44 FMC Bank B signals powered by 2.5V

 VREF_A_M2C, VREF_B_M2C and RES0

powered by VADJ

 Both VIO_B_M2C pins powered by 2.5V

 GA0, GA1, PG_M2C and PG_C2M powered by

3.3V

 60 Front I/O signals powered by 3.3V

 The 60 Front I/O LVTTL signals at the

VHDCI68/SCSI-V Connector are 5V tolerant

 On-board EEPROM contains IPMI hardware definition

 2.5V I/O voltage for Bank B provided to the Carrier

 Adjustable differential clock generator

 Operating temperature -40°C to +85°C

 MTBF (MIL-HDBK217F/FN2 GB 20°C)

TFMC900-10R: 655000 h

Order Information

RoHS Compliant

TFMC900-10R

Test FMC, test ANSI/VITA 57.1 FMC Carriers during development or series production, HPC-FMC, VHD68

connector

For the availability of non-RoHS compliant (leaded solder) products please contact TEWS.

Documentation

TFMC900-DOC User Manual

TEWS TECHNOLOGIES GmbH keeps the right to change technical specification without further notice.

All trademarks mentioned are property of their respective owners.

Issue 1.0.1

2017-08-24

TEWS TECHNOLOGIES GmbH

Am Bahnhof 7

25469 Halstenbek, Germany

Phone: +49 (0) 4101 4058 0

Fax: +49 (0) 4101 4058 19

e-mail: info@tews.com

www.tews.com