CS4239 datasheet(39/98 Pages) CIRRUS

39 / 98 page

XCTL1-XCTL0 XCTL Control: These bits are reflected

on the XCTL1,0 pins of the part.

NOTE: XCTL1 is multiplexed with

other functions; therefore, it may not

be available on a particular design.

0 - TTL logic low on XCTL1,0 pins

1 - TTL logic high on XCTL1,0 pins

Error Status and Initialization (I11, Read Only)

Default = 00000000

COR

PUR

ACI

DRS

ORR1

ORR0

ORL1

ORL0

ORL1-ORL0

Overrange Left Detect: These bits

determine the overrange on the left

ADC channel. These bits are up-

dated on a sample by sample basis.

0 - Less than -1.5 dB

1 - Between -1.5 dB and 0 dB

2 - Between 0 dB and 1.5 dB

overrange

3 - Greater than 1.5 dB overrange

ORR1-ORR0

Overrange Right Detect: These bits

determine the overrange on the

Right ADC channel.

0 - Less than -1.5 dB

1 - Between -1.5 dB and 0 dB

2 - Between 0 dB and 1.5 dB

overrange

3 - Greater than 1.5 dB overrange

DRS

DRQ Status: This bit indicates the

current status of the DRQs assigned

to the WSS Codec.

0 - Capture AND Playback DRQs are

presently inactive

1 - Capture OR Playback DRQs are

presently active

ACI

Auto-calibrate In-Progress: This bit

indicates the state of calibration.

0 - Calibration not in progress

1 - Calibration is in progress

PUR

Playback underrun: This bit is set

when playback data has not arrived

from the host in time to be played.

As a result, if DACZ = 0, the last

valid sample will be sent to the

DACs. This bit is set when an error

occurs and will not clear until the

Status register (R2) is read.

COR

Capture overrun: This bit is set when

the capture data has not been read

by the host before the next sample

arrives. The old sample will not be

overwritten and the new sample will

be ignored. This bit is set when an

error condition occurs and will not

clear until the Status register (R2) is

read.

The SER bit in the Status register (R2) is simply

a logical OR of the COR and PUR bits. This

enables a polling host CPU to detect an error

condition while checking other status bits.

MODE and ID (I12)

Default = 100x1010

CMS1

CMS0

res

1010

res

Reserved. Must write 0. Could read

as 0 or 1.

CMS1,0

Codec Mode Select bits: Enables the

Extended registers and functions of

the part.

00 - MODE 1

01 - Reserved

10 - MODE 2

11 - MODE 3

Reserved (I13)

Default = xxxxxxxx

rbc

res

rbc

Reserved, backwards compatible.

res

Reserved. Must write 0. Could read

as 0 or 1.

DS253PP2

CS4239

CrystalClear Portable ISA Audio System

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