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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC312XDP512F0MPVR датащи(PDF) 116 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 116 Page - Freescale Semiconductor, Inc |
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116 / 1350 page  Chapter 2 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev. 2.17 116 Freescale Semiconductor Figure 2-26. RESET Pin Tied to VDD (by a pull-up resistor) Figure 2-27. RESET Pin Held Low Externally 2.6 Interrupts The interrupts/reset vectors requested by the CRG are listed in Table 2-16. Refer to MCU specification for related vector addresses and priorities. 2.6.1 Real Time Interrupt The CRG generates a real time interrupt when the selected interrupt time period elapses. RTI interrupts are locally disabled by setting the RTIE bit to 0. The real time interrupt flag (RTIF) is set to1 when a timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit. The RTI continues to run during pseudo stop mode if the PRE bit is set to 1. This feature can be used for periodic wakeup from pseudo stop if the RTI interrupt is enabled. Table 2-16. CRG Interrupt Vectors Interrupt Source CCR Mask Local Enable Real time interrupt I bit CRGINT (RTIE) LOCK interrupt I bit CRGINT (LOCKIE) SCM interrupt I bit CRGINT (SCMIE) RESET Internal POR 128 SYSCLK 64 SYSCLK Internal RESET Clock Quality Check (no Self-Clock Mode) ) ( ) ( ) ( Clock Quality Check RESET Internal POR Internal RESET 128 SYSCLK 64 SYSCLK (no Self Clock Mode) ) ( ) ( ) ( |
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