SC312XDP512F0MPVR datasheet(111/1350 Pages) FREESCALE

111 / 1350 page

Chapter 2 Clocks and Reset Generator (S12CRGV6)

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

111

2.4.3.3.2

Wake-up from Full Stop (PSTP = 0)

The MCU requires an external interrupt or an external reset in order to wake-up from stop-mode.

If the MCU gets an external reset during full stop mode active, the CRG asynchronously restores all

conﬁguration bits in the register space to its default settings and will perform a maximum of 50 clock

check_windows (see Section 2.4.1.4, “Clock Quality Checker”). After completing the clock quality check

the CRG starts the reset generator. After completing the reset sequence processing begins by fetching the

normal reset vector. Full stop-mode is left and the MCU is in run mode again.

If the MCU is woken-up by an interrupt and the fast wake-up feature is disabled (FSTWKP = 0 or

SCME = 0), the CRG will also perform a maximum of 50 clock check_windows (see Section 2.4.1.4,

“Clock Quality Checker”). If the clock quality check is successful, the CRG will release all system and

core clocks and will continue with normal operation. If all clock checks within the Timeout-Window are

failing, the CRG will switch to self-clock mode or generate a clock monitor reset (CMRESET) depending

on the setting of the SCME bit.

If the MCU is woken-up by an interrupt and the fast wake-up feature is enabled (FSTWKP = 1 and

SCME = 1), the system will immediately resume operation in self-clock mode (see Section 2.4.1.4, “Clock

Quality Checker”). The SCMIF ﬂag will not be set. The system will remain in self-clock mode with

oscillator disabled until FSTWKP bit is cleared. The clearing of FSTWKP will start the oscillator and the

clock quality check. If the clock quality check is successful, the CRG will switch all system clocks to

oscillator clock. The SCMIF ﬂag will be set. See application examples in Figure 2-23 and Figure 2-24.

Because the PLL has been powered-down during stop-mode the PLLSEL bit is cleared and the MCU runs

on OSCCLK after leaving stop-mode. The software must manually set the PLLSEL bit again, in order to

switch system and core clocks to the PLLCLK.

NOTE

In full stop mode or self-clock mode caused by the fast wake-up feature, the

clock monitor and the oscillator are disabled.

SC312XDP512F0MPVR датащи(PDF) 111 Page - Freescale Semiconductor, Inc