SC312XDP512F0MPVR datasheet(820/1350 Pages) FREESCALE

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Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.17

820

Freescale Semiconductor

22.3.2

Table 22-3 summarizes the effect on the various configuration bits, data direction (DDR), output level

(IO), reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the ports.

The configuration bit PS is used for two purposes:

1. Conﬁgure the sensitive interrupt edge (rising or falling), if interrupt is enabled.

2. Select either a pull-up or pull-down device if PE is active.

NOTE

All register bits in this module are completely synchronous to internal

clocks during a register read.

Table 22-3. Pin Conﬁguration Summary

DDR

RDR

PS1

1 Always “0” on Port A, B, C, D, E, K, AD0, and AD1.

IE2

2 Applicable only on Port P, H, and J.

Function

Pull Device

Interrupt

Input

Disabled

Input

Pull Up

Disabled

Input

Pull Down

Disabled

Input

Disabled

Falling edge

Input

Disabled

Rising edge

Input

Pull Up

Falling edge

Input

Pull Down

Rising edge

Output, full drive to 0

Disabled

Output, full drive to 1

Disabled

Output, reduced drive to 0

Disabled

Output, reduced drive to 1

Disabled

Output, full drive to 0

Disabled

Falling edge

Output, full drive to 1

Disabled

Rising edge

Output, reduced drive to 0

Disabled

Falling edge

Output, reduced drive to 1

Disabled

Rising edge

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