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SC312XDP512F0MPVR датащи(PDF) 698 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 698 Page - Freescale Semiconductor, Inc |
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698 / 1350 page ![]() Chapter 19 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.17 698 Freescale Semiconductor 19.3.1.1 Debug Control Register 1 (DBGC1) Read: Anytime Write: Bits 7,1,0 anytime, Bit 6 can be written anytime but always reads back as 0. Bits 5:2 anytime DBG is not armed. NOTE When disarming the DBG by clearing ARM with software, the contents of bits[5:2] are not affected by the write, since up until the write operation, ARM=1 preventing these bits from being written. These bits must be cleared using a second write if required. 0x0029 DBGXAH R 0 Bit 22 21 20 19 18 17 Bit 16 W 0x002A DBGXAM R Bit 15 14 13 12 11 10 9 Bit 8 W 0x002B DBGXAL R Bit 7 654321 Bit 0 W 0x002C DBGXDH R Bit 15 14 13 12 11 10 9 Bit 8 W 0x002D DBGXDL R Bit 7 654321 Bit 0 W 0x002E DBGXDHM R Bit 15 14 13 12 11 10 9 Bit 8 W 0x002F DBGXDLM R Bit 7 654321 Bit 0 W 0x0020 76543210 R ARM 0 XGSBPE BDM DBGBRK COMRV W TRIG Reset 00000000 Figure 19-3. Debug Control Register (DBGC1) Address Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved Figure 19-2. DBG Register Summary (continued) |
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