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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC312XDP512F0MPVR датащи(PDF) 345 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 345 Page - Freescale Semiconductor, Inc |
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345 / 1350 page  Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 345 7.3.2.27 16-Bit Pulse Accumulator B Control Register (PBCTL) Read: Anytime Write: Anytime All bits reset to zero. 000001118 00001111 16 00011111 32 00111111 64 01111111 128 11111111 256 76543210 R0 PBEN 0000 PBOVI 0 W Reset 00000000 = Unimplemented or Reserved Figure 7-49. 16-Bit Pulse Accumulator B Control Register (PBCTL) Table 7-35. PBCTL Field Descriptions Field Description 6 PBEN Pulse Accumulator B System Enable — PBEN is independent from TEN. With timer disabled, the pulse accumulator can still function unless pulse accumulator is disabled. 0 16-bit pulse accumulator system disabled. 8-bit PAC1 and PAC0 can be enabled when their related enable bits in ICPAR are set. 1 Pulse accumulator B system enabled. The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse accumulator B. When PACB is enabled, the PACN1 and PACN0 registers contents are respectively the high and low byte of the PACB. PA1EN and PA0EN control bits in ICPAR have no effect. The PACB shares the input pin with IC0. 1 PBOVI Pulse Accumulator B Overflow Interrupt Enable 0 Interrupt inhibited 1 Interrupt requested if PBOVF is set Table 7-34. Precision Timer Modulus Counter Prescaler Select Examples when PRNT = 1 (continued) PTMPS7 PTMPS6 PTMPS5 PTMPS4 PTMPS3 PTMPS2 PTMPS1 PTMPS0 Prescaler Division Rate |
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