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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC312XDP512F0MPVR датащи(PDF) 335 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 335 Page - Freescale Semiconductor, Inc |
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335 / 1350 page  Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 335 Read: Anytime Write: Anytime All bits reset to zero. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse accumulator. When PACA in enabled (PAEN = 1 in PACTL), the PACN3 and PACN2 registers contents are respectively the high and low byte of the PACA. When PACN3 overflows from 0x00FF to 0x0000, the interrupt flag PAOVF in PAFLG is set. Full count register access will take place in one clock cycle. NOTE A separate read/write for high byte and low byte will give a different result than accessing them as a word. When clocking pulse and write to the registers occurs simultaneously, write takes priority and the register is not incremented. 7.3.2.18 Pulse Accumulators Count Registers (PACN1 and PACN0) Read: Anytime Write: Anytime All bits reset to zero. The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse accumulator. When PACB in enabled, (PBEN = 1 in PBCTL) the PACN1 and PACN0 registers contents are respectively the high and low byte of the PACB. 76543210 R PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 W Reset 00000000 Figure 7-38. Pulse Accumulators Count Register 2 (PACN2) 76543210 R PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) PACNT1(9) PACNT0(8) W Reset 00000000 Figure 7-39. Pulse Accumulators Count Register 1 (PACN1) 76543210 R PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 W Reset 00000000 Figure 7-40. Pulse Accumulators Count Register 0 (PACN0) |
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