SC312XDP512F0MPVR datasheet(207/1350 Pages) FREESCALE

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Chapter 6 XGATE (S12XGATEV2)

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

207

•

Single Stepping

Writing a "1" to the XGSS bit will call the RISC core to execute a single instruction. All RISC core

registers will be updated accordingly.

•

Write accesses to the XGCHID register

Three operations can be performed by writing to the XGCHID register:

– Change of channel ID

If a non-zero value is written to the XGCHID while a thread is active (XGCHID

≠ $00), then

the current channel ID will be changed without any inﬂuence on the program counter or the

other RISC core registers.

– Start of a thread

If a non-zero value is written to the XGCHID while the XGATE is idle (XGCHID = $00),

then the thread that is associated with the new channel ID will be executed upon leaving

debug mode.

– Termination of a thread

If zero is written to the XGCHID while a thread is active (XGCHID

≠ $00), then the current

thread will be terminated and the XGATE will become idle.

6.6.2

Entering Debug Mode

Debug mode can be entered in four ways:

1. Setting XGDBG to "1"

Writing a "1" to XGDBG and XGDBGM in the same write access causes the XGATE to enter

debug mode upon completion of the current instruction.

NOTE

After writing to the XGDBG bit the XGATE will not immediately enter

debug mode. Depending on the instruction that is executed at this time there

may be a delay of several clock cycles. The XGDBG will read "0" until

debug mode is entered.

2. Software breakpoints

XGATE programs which are stored in the internal RAM allow the use of software breakpoints. A

software breakpoint is set by replacing an instruction of the program code with the "BRK"

instruction.

As soon as the program execution reaches the "BRK" instruction, the XGATE enters debug mode.

Additionally a software breakpoint request is sent to the S12X_DBG module (see section 4.9 of

the S12X_DBG Section).

Upon entering debug mode, the program counter will point to the "BRK" instruction. The other

RISC core registers will hold the result of the previous instruction.

To resume program execution, the "BRK" instruction must be replaced by the original instruction

before leaving debug mode.

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