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CMOS High Voltage Logic – CD4073B

Rev 1.0

15/03/18

Switching Waveform

Figure 1 – Propagation Delay, Output Timing

5. Not production tested in die form, characterized by chip design and tested in package.

LIMITS

PARAMETER

SYMBOL

VDD

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

5V

VOL = 0.4V

0.64

0.51

0.36

10V

VOL = 0.5V

1.6

1.3

0.9

Minimum Output

(Sink) Current

IOL

15V

VOL = 1.5V

4.2

3.4

2.4

mA

Maximum Input

Leakage Current

IIN

15V

VIN = VDD or VSS

±0.1

±0.1

±1.0

µA

5V

0.25

0.25

7.5

10V

0.5

0.5

15

Maximum Quiescent

Current

IDD

15V

VIN = VDD or VSS

1.0

1.0

30

µA

 

DC Electrical Characteristics (Voltages referenced to V

SS)

LIMITS

PARAMETER

SYMBOL

VDD

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

5V

250

250

500

10V

120

120

240

Maximum

Propagation Delay,

Input to Output

(Figure 1)

tPLH, tPHL

15V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

90

90

180

ns

5V

200

200

400

10V

100

100

200

Maximum Output

Transition Time, Any

Output (Figure 1)

tTLH, tTHL

15V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

80

80

160

ns

TYPICAL

Maximum Input

Capacitance

CIN

-

TA = 25°C

VIN = 0V

-

5

-

pF

AC Electrical Characteristics5