Data Brief

For further information contact your local STMicroelectronics sales office.

October 2007

Rev 2

1/5

5

STA2062

Cartesio™

Infotainment application processor with embedded GPS

Features

– Cache: 16KByte instruction, 16KByte data

–

8KByte instruction TCM (tightly coupled memory)

– 8KByte data TCM

– 32KByte embedded ROM for boot

– Two banks of 64KByte embedded SRAM

– 512Byte embedded SRAM for back-up

– 4GByte total linear address space

– Memory extension through:

Flexible static memory controller-FSMC

(NOR/NAND Flash, CF/CF+, ROM, SRAM

support)

Mobile DDR/SDRAM controller:

16bit data @166MHz, 2 Chip Select,

512Kbit each

– 64-channel interrupt controller (VIC)

– 16-vectorized interrupts with 16

programmable priority Level

– Two 8-channel double port system DMA

controllers

– 32 DMA request for each controller

– Two external DMA requests are supported

embedded subsystem

input capture/output compare and PWM

receive FIFO with DMA and hardware flow control

separate transmit and receive FIFO with

Motorola-SPI, National-MicroWire and Texas-

SSI support modes

separate transmit and receive FIFO

(ULPI interface)

integrated 1.1 physical layer transceiver

Interface (SD/SDIO/MMC) up to 8 bit data

embedded medium trace module

2.5 ±10%V

– LFBGA16x16x1.4mm (19x19balls)

– 0.8mm ball pitch, (0.4mm ball)

– Full array

Table 1.

Device summary

Order code

Package

Packing

STA2062

LFBGA361

Tray

LFBGA361 (16x16x1.4mm)

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