R8821

R

R

16-BIT RISC MICROCONTROLLER

Specifications subject to change without notice, contact your sales representatives for the most update information.

Page 2 of 5

REV 1.0 Jul.11 2006

1.

Features

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CPU Core

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RDC’s proprietary RISC architecture

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Five-stage pipeline

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CPU clock speed: 40MHz

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Supports CPU ID

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Supports 32 PIO pins

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Static & synthesizable design

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Bus Interface

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Multiplexed address and data bus

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Supports a non-multiplexed address bus A[19:0]

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8-bit or 16-bit external bus dynamic access

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ROM/RAM/DRAM Controller and Addressing

Space

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1M-byte memory address space

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64K-byte I/O space

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With 8-bit or 16-bit boot ROM bus size

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Supports 64Kx16, 128Kx16, 256Kx16 EDO or FP

DRAM with auto-refresh control

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Two independent DMA channels

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Asynchronous Serial Channels

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Supports two asynchronous serial channels with

hardware handshaking signals

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Interrupt Controller

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The Interrupt controller with seven maskable

external interrupts and one non-maskable

external interrupt

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Programmable Chip-select Logic

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Programmable chip-select logic for memory or

I/O bus cycle decoder

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Programmable Wait-state Generators

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Counters/Timers

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Three independent 16-bit timers and one

independent programmable watchdog timer

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Software Compatible with the 80C186

Microprocessor

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Operating Voltage Range

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Core voltage: 5V ± 10%

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I/O voltage: 5V ± 10%

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Ambient Temperature: 0 ~ +70

°C

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Package Type

-100-pin PQFP &

100-pin LQFP