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Xin

Xout

Vctr

VCXO

XO

20pF

20pF

i.e.

XCSEL =10pF

CDCE913

CDCEL913

SCAS849A – JUNE 2007 – REVISED AUGUST 2007

Table 9. Generic Configuration Register

Offset

(1)

Bit

(2)

Acronym

Default

(3)

Description

7

E_EL

Xb

Device identification (read-only): 1 is CDCE913 (3.3 V out), 0 is CDCEL913 (1.8 V out)

00h

6:4

RID

0h

Revision Identification Number (read only)

3:0

VID

1h

Vendor Identification Number (read only)

7

–

0b

Reserved – always write 0

0 – EEPROM programming is completed

6

EEPIP

0b

EEPROM Programming Status4:

1 – EEPROM is in programming mode

0 – EEPROM is not locked

5

EELOCK

0b

Permanently Lock EEPROM Data

(5)

1 – EEPROM will be permanently locked

Device Power Down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)

01h

4

PWDN

0b

0 – device active (PLL1 and all outputs are enabled)

1 – device power down (PLL1 in power down and all outputs in 3-state)

00 – Xtal

10 – LVCMOS

3:2

INCLK

00b

Input clock selection:

01 – VCXO

11 – reserved

1:0

SLAVE_ADR

01b

Address Bits A0 and A1 of the Slave Receiver Address

7

M1

1b

Clock source selection for output Y1:

0 – input clock

1 – PLL1 clock

Operation mode selection for pin 12/13

(6)

6

SPICON

0b

0 – serial programming interface SDA (pin 13) and SCL (pin 12)

1 – control pins S1 (pin 13) and S2 (pin 12)

02h

5:4

Y1_ST1

11b

Y1-State0/1 Definition

00 – device power down (all PLLs in power down and all

10 – Y1 disabled to low

3:2

Y1_ST0

01b

outputs in 3-State)

11 – Y1 enabled

01 – Y1 disabled to 3-state

1:0

Pdiv1 [9:8]

0 – divider reset and stand-by

001h

10-Bit Y1-Output-Divider Pdiv1:

1-to-1023 – divider value

03h

7:0

Pdiv1 [7:0]

7

Y1_7

0b

6

Y1_6

0b

5

Y1_5

0b

4

Y1_4

0b

0 – State0 (predefined by Y1_ST0)

04h

Y1_x State Selection

(7)

1 – State1 (predefined by Y1_ST1)

3

Y1_3

0b

2

Y1_2

0b

1

Y1_1

1b

0

Y1_0

0b

Crystal Load Capacitor Selection

(8)

00h

→ 0 pF

01h

→ 1 pF

02h

→ 2 pF

7:3

XCSEL

0Ah

:14h-to-1Fh

→ 20 pF

05h

2:0

0b

Reserved – do not write other than 0

7-Bit Byte Count (defines the number of bytes which will be sent from this device at the next Block Read transfer); all bytes

7:1

BCOUNT

20h

have to be read out to correctly finish the read cycle.

06h

0– no EEPROM write cycle

0

EEWRITE

0b

Initiate EEPROM Write Cycle

(4) (9)

1 – start EEPROM write cycle (internal register are saved to the EEPROM)

(1)

Writing data beyond ‘20h’ may affect device function.

(2)

All data transferred with the MSB first.

(3)

Unless customer-specific setting.

(4)

During EEPROM programming, no data is allowed to be sent to the device via the SDA/SCL bus until the programming sequence is

completed. Data, however, can be read out during the programming sequence (Byte Read or Block Read).

(5)

If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. No further programming is possible.

Data, however can still be written via SDA/SCL bus to the internal register to change device function on the fly. But new data can no

longer be saved to the EEPROM. EELOCK is effective only, if written into the EEPROM.

(6)

Selection of “control pins” is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are

(SDA/SCL), and the two slave receiver address bits are reset to A0=”0” and A1=“0”.

(7)

These are the bits of the Control Terminal Register (see Table 8). The user can predefine up to eight different control settings. These

settings then can be selected by the external control pins, S0, S1, and S2.

(8)

The internal load capacitor (C1, C2) has to be used to achieve the best clock performance. External capacitors should be used only to

finely adjust CL by a few picofarads. The value of CL can be programmed with a resolution of 1 pF for a crystal load range of 0 pF to 20

pF. For CL > 20 pF, use additional external capacitors. Also, the value of the device input capacitance has to be considered which

always adds 1.5 pF (6 pF//2 pF) to the selected CL. For more information about VCXO configuration and crystal recommendation, see

application report SCAA085.

(9)

The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The

EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level high does not trigger an EEPROM WRITE cycle. The

EEWRITE bit has to be reset to low after the programming is completed. The programming status can be monitored by reading out

EEPIP. If EELOCK is set to high, no EEPROM programming is possible.

Copyright © 2007, Texas Instruments Incorporated

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