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Clock Inputs

ADS5474

AVDD5

CLK

CLK

GND

AVDD5

GND

GND

1kW

1kW

~2.4V

Parasitic

~200fF

Parasitic

~200fF

Clock

Buffer

CLK

ADS5474

CLK

SquareWaveor

SineWave

0.01

F

m

0.01

F

m

ClockAmplitude

V

90

85

80

75

70

65

60

0

0.5

1.0

1.5

5.0

2.0

2.5

3.0

f =400MSPS

f

=230MHz

S

IN

3.5

4.0

4.5

SFDR(dBc)

SNR(dBFS)

ADS5474

SLAS525 – JULY 2007

Applications Information (continued)

The ADS5474 clock input can be driven with either a differential clock signal or a single-ended clock input, as

clock amplitude becomes more of a factor in performance as the analog input frequency increases. In

low-input-frequency applications, where jitter may not be a big concern, the use of a single-ended clock (as

shown in Figure 41) could save cost and board space without much performance tradeoff. When clocked with

this configuration, it is best to connect CLK to ground with a 0.01-

μF capacitor, while CLK is ac-coupled with a

0.01-

μF capacitor to the clock source, as shown in Figure 41.

Figure 40. Clock Input Circuit

Figure 41. Single-Ended Clock

Figure 42. AC Performance versus Clock Level

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