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GL830 датащи(PDF) 15 Page - GENESYS LOGIC |
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GL830 датащи(HTML) 15 Page - GENESYS LOGIC |
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15 / 29 page ![]() GL830 USB2.0 to SATA Bridge Controller ©2007 Genesys Logic Inc. - All rights reserved. Page 15 26 DD4 B 58 DIOR_ B 90 GND P 122 ROM_A8 O 27 ROM_A2 O 59 T_ROM I 91 VDD P 123 ROM_A7 O 28 DD11 B 60 IORDY B 92 X2 B 124 ROM_A9 O 29 ROM_A14 O 61 GPIO1 B 93 X1 I 125 ROM_A6 O 30 DD3 B 62 DMACK_ B 94 VDD P 126 ROM_A10 O 31 ROM_A1 O 63 PHYRDY O 95 GND P 127 ARESET_ B 32 DD12 B 64 GPIO4 B 96 RTERM A 128 SPDSEL I 3.3 Pin Descriptions Table 3.4 – 48 Pin Descriptions USB Interface Pin Name Pin# Type Description RREF 23 A Reference resistor DM 25 B HS D- DP 26 B HS D+ AVDD 22,27 P USB Analog 3.3V power AGND 24,28 P USB Analog Ground SATA Interface Pin Name Pin# Type Description RTERM 37 A Reference resistor PLLVDD 38 P 1.8V Power Supplies for internal PLL PLLVSS 39 P Ground for internal PLL TXVSS 40 P Ground for transceiver part TXVDD 41 P 1.8V Power Supplies for transceiver part TXP 42 O SATA Differential Transmit TX+ TXN 43 O SATA Differential Transmit TX- RXN 44 I SATA Differential Receive RX- RXP 45 I SATA Differential Receive RX+ RXVDD 46 P 1.8V Power Supplies for receiver part RXVSS 47 P Ground for receiver part Digital Power and Ground Pin Name Pin# Type Description |
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