TMS320VC5510 datasheet(16/90 Pages) TI

16 / 90 page

Introduction

June 2000 − Revised September 2007

SPRS076O

2.3

Signal Descriptions

Table 2−2 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for exact

pin locations based on package type.

Table 2−2. Signal Descriptions

SIGNAL

NAME

TYPE†

OTHER‡

DESCRIPTION

EMIF - ADDRESS BUS

A[21:0]

O/Z

E,F

External memory address bus (byte address). Address all external memory (program and

data). Since A[23:22] are redundant to the CE[3:0] memory space selects in terms of memory

addressing capability, A[23:22] are not externally provided.

EMIF - CONTROL SIGNALS COMMON TO ALL MEMORY TYPES

CE0

CE1

CE2

CE3

O/Z

E,F

External memory space enables. Select one of four external memory ranges based on the

address.

BE0

BE1

BE2

BE3

O/Z

E,F

Byte-enable control. Can be used as chip selects for external memory. These signals respond

according to the data width of the memory access. 8-bit accesses cause a single byte enable to

respond. 16-bit accesses cause two byte enables to respond. 32-bit accesses cause all four byte

enables to respond.

CLKMEM

O/Z

E,F

Memory interface clock (for SDRAM / SBSRAM). Clock for synchronizing the external

synchronous memories to the C55x external memory interface.

EMIF - DATA BUS

D[31:0]

I/O/Z

D,E,F

External data bus. Provides data exchange between external memories and the C55x external

memory interface.

The bus holders on D[31:0] are controlled by the BH bit in the system register (SYSR).

EMIF - BUS ARBITRATION

HOLD

−

Hold request. HOLD is asserted by an external host to request control of the address, data and

control signals.

HOLDA

O/Z

Hold acknowledge. HOLDA is asserted by the DSP to indicate that the DSP is in the HOLD state

and that the EMIF address, data and control signals are in a high-impedance state, allowing the

external memory interface to be accessed by other devices.

EMIF - ASYNCHRONOUS MEMORY CONTROL SIGNALS

ARE

Asynchronous memory read enable. ARE acts as a strobe during asynchronous memory reads

only.

AOE

O/Z

E,F

Asynchronous memory output enable. AOE indicates whether a memory access is a read

(low) or a write (high).

AWE

Asynchronous memory write enable. AWE acts as a strobe during asynchronous memory

writes only.

ARDY

Asynchronous memory ready input. ARDY indicates that an external device is ready for a bus

transaction to be completed. If the device is not ready (ARDY is low), the processor extends the

memory access by one cycle and checks ARDY again. The ARDY signal is sampled at the end

of the STROBE period in the memory access.

† I = Input, O = Output, S = Supply, Z = High impedance

‡ Other Pin Characteristics:

A − Internal pullup (always enabled)

E − Pin is high impedance in HOLD mode (due to HOLD pin).

B − Internal pulldown (always enabled)

F − Pin is high impedance in OFF mode (due to EMU1/OFF pin).

C − Hysteresis input

G − Pin can be configured as a general-purpose input.

D − Pin has bus holder

H − PIn can be configured as a general-purpose output.

J − Internal pullup enabled by the HPE bit in the system register (SYSR)

K − Internal pulldown enabled by the HPE bit in the system register (SYSR)

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