ST10F273 datasheet(162/179 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F273

162/179

24.8.17

Demultiplexed bus

VDD = 5V ± 10%, VSS = 0V, TA = –40°C to +125°C, CL = 50pF,

ALE cycle time = 4 TCL + 2tA + tC + tF (50ns at 40 MHz CPU clock without wait states)

Table 78.

Demultiplexed bus timings

Symbol

Parameter

FCPU = 40 MHz

TCL = 12.5 ns

Variable CPU Clock

1/2 TCL = 1 to 64 MHz

Min.

Max.

Min.

Max.

ALE high time

4 + tA

–

TCL – 8.5 + tA

–ns

Address setup to ALE

1.5 + tA

–

TCL – 11 + tA

–ns

t80

Address/Unlatched CS

setup to RD, WR

(with RW-delay)

12.5 + 2tA

–

2TCL – 12.5

+ 2tA

–ns

t81

Address/Unlatched CS

setup to RD, WR

(no RW-delay)

0.5 + 2tA

–

TCL – 12 + 2tA

–ns

t12

RD, WR low time

(with RW-delay)

15.5 + tC

–

2TCL – 9.5 + tC

–ns

t13

RD, WR low time

(no RW-delay)

28 + tC

–

3TCL – 9.5 + tC

–ns

t14

RD to valid data in

(with RW-delay)

–6 + tC

–

2TCL – 19 + tC

t15

RD to valid data in

(no RW-delay)

–

18.5 + tC

–

3TCL – 19 + tC

t16

ALE low to valid data in

–

17.5 + tA + tC

–

3TCL – 20 + tA + tC

t17

Address/Unlatched CS to

valid data in

–

20 + 2tA + tC

–

4TCL – 30 + 2tA + tC

t18

Data hold after RD

rising edge

0–

–

t20

Data float after RD rising

edge (with RW-delay)3(1)

–

16.5 + tF

–

2TCL – 8.5 + tF + 2tA

t21

Data float after RD rising

edge (no RW-delay) (1)

–4 + tF

–

TCL – 8.5 + tF + 2tA

t22

Data valid to WR

10 + tC

–

2TCL – 15 + tC

–ns

t24

Data hold after WR

4 + tF

–

TCL – 8.5 + tF

–ns

t26

ALE rising edge after RD,

–10 + tF

–

–10 + tF

–ns

t28

Address/Unlatched CS

hold after RD, WR (2)

0 + tF

–0 + tF

–ns

t28h CC

Address/Unlatched CS

hold after WRH

– 5 + tF

–– 5 + tF

–ns

t38

ALE falling edge to

Latched CS

– 4 – tA

6 – tA

– 4 – tA

6 – tA

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