ST10F272 datasheet(141/179 Pages) STMICROELECTRONICS

141 / 179 page

ST10F272

Electrical characteristics

141/179

besides, it sources charge during the sampling phase, when the analog signal source is a

high-impedance source.

A real filter, can typically be obtained by using a series resistance with a capacitor on the

input pin (simple RC Filter). The RC filtering may be limited according to the value of source

impedance of the transducer or circuit supplying the analog signal to be measured. The filter

at the input pins must be designed taking into account the dynamic characteristics of the

input signal (bandwidth).

Figure 40.

A/D converter input pins scheme

Input Leakage and external circuit

The series resistor utilized to limit the current to a pin (see RL in Figure 40), in combination

with a large source impedance can lead to a degradation of A/D converter accuracy when

input leakage is present.

Data about maximum input leakage current at each pin are provided in the Data Sheet

(Electrical Characteristics section). Input leakage is greatest at high operating temperatures,

and in general it decreases by one half for each 10°C decrease in temperature.

Considering that, for a 10-bit A/D converter one count is about 5mV (assuming VAREF = 5V),

an input leakage of 100nA acting though an RL = 50kΩ of external resistance leads to an

error of exactly one count (5mV); if the resistance were 100k

Ω the error would become two

counts.

Eventual additional leakage due to external clamping diodes must also be taken into

account in computing the total leakage affecting the A/D converter measurements. Another

contribution to the total leakage is represented by the charge sharing effects with the

sampling capacitance: being CS substantially a switched capacitance, with a frequency

equal to the conversion rate of a single channel (maximum when fixed channel continuous

conversion mode is selected), it can be seen as a resistive path to ground. For instance,

assuming a conversion rate of 250kHz, with CS equal to 4pF, a resistance of 1MΩ is

obtained (REQ = 1 / fCCS, where fC represents the conversion rate at the considered

channel). To minimize the error induced by the voltage partitioning between this resistance

(sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit

must be designed to respect the following relation:

RSW

CP2

VDD

Sampling

Source

Filter

Current Limiter

EXTERNAL CIRCUIT

INTERNAL CIRCUIT SCHEME

RS Source Impedance

RF Filter Resistance

CF Filter Capacitance

RL Current Limiter Resistance

RSW Channel Selection Switch Impedance

RADSampling Switch Impedance

CP Pin Capacitance (two contributions, CP1 and CP2)

CS Sampling Capacitance

CP1

RAD

Channel

Selection

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⋅

---LSB

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