Specifications ispLSI 3448

9

ispLSI 3448 Timing Model

Derivations of

=

=

=

=

Logic + Reg su - Clock (min)

(

(#24+ #30+ #35) + (#38) - (#24+ #30+ #44)

(2.3 + 3.2 + 5.0) + (1.5) - (2.3 + 3.2 + 3.7)

=

=

=

=

Clock (max) + Reg h - Logic

(

(#24+ #30+ #44) + (#39) - (#24+ #30+ #35)

(2.3 + 3.2 + 3.7) + (5.4) - (2.3 + 3.2 + 5.0)

=

=

=

=

Clock (max) + Reg co + Output

(

(#24 + #30 + #44) + (#40) + (#45 + #47)

(2.3 + 3.2 + 3.7) + (0.5) + (1.5 + 2.5)

Table 2-0042/3448

2.8 ns

4.1 ns

13.7 ns

GLB Reg

Delay

I/O

(Output)

ORP

Delay

Feedback

4 PT Bypass

20 PT

XOR Delays

Control

PTs

Input

Register

I/O

(Input)

Y0,1,2

Y3,4

D

Q

GRP

GLB Reg Bypass

ORP Bypass

DQ

RST

RE

OE

CK

I/O Reg Bypass

I/O Cell

ORP

GLB

GRP

I/O Cell

#25 - 29

#30

#33

#32

#31

#34 - 36

#42 - 44

#51

#54

#55

#45

#46

Reset

#24

#52

RST

#53

#53

#37

#38 - 41

#49, 50

#47, 48

GOE0,1

TOE

0902/3448

Note: Calculations are based on timing specs for the ispLSI 3448-90L.