TMS320DM6437 datasheet(7/309 Pages) TI

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Revision History

TMS320DM6437

Digital Media Processor

SPRS345B – NOVEMBER 2006 – REVISED MARCH 2007

This data manual revision history highlights the technical changes made to the SPRS345A device-specific

data manual to make it an SPRS345B revision.

Scope: Applicable updates to the DM643x DMP device family, specifically relating to the TMS320DM6437

device, have been incorporated.

Upon exit from the bootloader code, all C64x+ memories are configured as all RAM, Cache is disabled.

SEE

ADDITIONS/MODIFICATIONS/DELETIONS

Global

Updated/Changed documentation references to User's Guide, Reference Guides, and Application Reports

Global

Updated/Changed "Flashboot" to "Flash Boot"

Global

Updated/Changed "EM_WAIT" signal name to "EM_WAIT/(RDY/BSY)" where applicable

Global

Updated/Changed "HCNTL[B], HCNTL[A]" to "HCNTL[1:0]"

Global

Updated/Changed all references to "PLLC0" and "PLLC1" to "PLLC1" and "PLLC2"

Global

Deleted all references to "System Reset". This device does not support System Reset.

Global

General-Purpose Input/Output (GPIO) pins shall be referred to as GP[x]. Register bit fields and interrupt

acronmys may be different (e.g., GPIO01 interrupt)

Section 1.1

Section 1.1, Features:

Deleted "/Debug" from the "Fully Software-Compatible With C64x" feature

Section 2.1

Section 2.1, Device Characteristics:

Table 2-1, Characteristics of the DM6437 Processor:

Updated/Changed PLL Options "CLKIN1 frequency multiplier (27 MHz reference)" to "MXI/CLKIN

frequency multiplier (27 MHz reference)"

Updated/Changed the "Cycle Time" for -400 speed device from "2.22 ns" to "2.5 ns"

Section 2.4

Section 2.4, Memory Map Summary:

Table 2-3, Memory Map Summary:

Updated/Changed "For all boot modes that default to ..." footnote

Table 2-4, Configuration Memory Map Summary:

Deleted 0x01BC 0000 — 0x01BC 00FF AET Registers; now "Reserved"

Section 3.4.1

Section 3.4.1, Boot Modes:

Deleted "sampled at device reset (once RESET or POR is de-asserted)" from the to the "The DM6437

boot modes are ..." paragraph

Added "For information on how ..." sentence to the "The DM6437 boot modes are ..." paragraph

Table 3-5, Non-Fastboot Modes (FASTBOOT = 0):

Added "For all boot modes that default to ..." footnote

Table 3-6, Fixed-Multiplier Fastboot Modes (FASTBOOT = 1, AEM[2:0] = 001b):

Added "For all boot modes that default to ..." footnote

Table 3-7, User-Select Multiplier Fastboot Modes (FASTBOOT = 1, AEM[2:0] = 000b, 011b, 100b, or

101b):

Added "For all boot modes that default to ..." footnote

Section 3.4.1

Section 3.4.1, Boot Modes:

Internal Bootloader ROM (0x0010 0000) bullet:

Added Note:

Section 3.4.1.5

Section 3.4.1.5, Host Boot Modes:

Updated/Changed from "Note: the HPI HSTROBE pulse duration timing requirement [tw(HSTBL)] is ..." to

"Note: the HPI HSTROBE inactive pulse duration timing requirement [tw(HSTBH)] is ..."

Section 3.4.2.1

Section 3.4.2.1, BOOTCFG Register:

Deleted "at RESET or POR de-asserted (high)" from the "The Device Bootmode ..." paragraph

Added "sampled at device reset. For information on how ..." to the "The Device Bootmode ..." paragraph

Table 3-9, BOOTCFG Register Description:

Deleted '[default]" from the "PLLMS" description "... 8-bit EMIFA (Async) Pinout Mode 1 Address Width ..."

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Revision History

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