HT9480 datasheet(16/47 Pages) HOLTEK

16 / 47 page

HT9480

Rev. 1.20

July 31, 2002

On the other hand, in the pulse width measurement

mode with the TON bit equal to one, when the TMR1 re-

ceives a transient from low to high (or high to low de-

pending upon the TE bit) it will start counting until the

TMR1 returns to the original level and resets the TON as

well. The measured result will remain in the timer/event

counter even when the activated transient occurs again.

In other words, only one cycle measurement can be

made until the TON is set. The cycle measurement will

re-function as long as further transient pulses are re-

ceived. Note that, in this operation mode, the

timer/event counter starts counting not according to the

logic level but to the transient edges. In the case of

counting overflows, the counter is re-loaded from its

counter preload register and issues an interrupt request,

similar to the other two modes.

To enable the counting operation, the value of the timer

on bit (TON; bit 4 of TMRC0 and TMRC1) is

²1².Inthe

pulse width measurement mode, the TON is automati-

cally cleared after the measurement cycle is completed.

In the other two modes, namely the event count or timer

mode, the TON can be reset only by instructions. The

overflow of the programmable timer counter and of the

timer/event counter can be configured as one of the

wake-up sources. No matter what type of operation

mode is chosen, writinga0to ET0I and ET1I disables

the interrupt service of the programmable timer counter

and the timer/event counter, respectively.

In the case of the programmable timer counter and a

timer/event counter OFF condition, writing data to their

preload registers also reloads that data to their coun-

ters. But if the programmable timer counter or the

timer/event counter is turned on, data written to the

counter is kept only in its preload register, and the coun-

ter still goes on operating until an overflow occurs.

After the counter (reading TMR0 or TMR1) is read, the

clock is blocked to avoid errors. The programmer should

take clock blocking into consideration, since this may re-

sult in timing counting errors.

Programmable tone generator

The programmable tone generator is implemented in

the HT9480. The programmable tone generator con-

tains an 8-stage programmable frequency divider (map-

ping to the 1DH address of the MCU), a 4-stage

programmable frequency prescaler (set by SPF10 and

SPF11), and a frequency source selector (set by

SPF17). When 1DH=00H, the tone generator is dis-

abled and BZ outputs high. But when 1DH is of any

value greater than zero the generator is enabled. The

value of the frequency divider, ranging from 2~256, is al-

ways greater than the assigned value by 1. The output

of the 8-stage divider is divided by 2 to generate an out-

put of (1/2 or 1/4) duty cycle on BZ. The 4-stage pro-

grammable frequency prescaler is shown below.

SPF10

SPF11

Prescaler Divider Factor

The above setting of the prescaler divider factor is de-

signed for applications on melodies or sound effects.

The frequency source selector is set by SPF17. When

SPF17=0, the value of the frequency source selector is

the system clock. On the other hand, when SPF17=1,

the value of the selector turns out to be 32.768kHz. For

instance, if the desired output of BZ is 2.73kHz, the fre-

quency source is 32.768kHz, the values of SPF10 and

SPF11 are both set to 0, and the value of the program-

mable frequency divider is set to 5.

Input/Output ports

There are 7 input lines, and 10 input/output lines in the

HT9480, which are labeled as PA, and PB; PC (PC0,

PC1). These are mapped to [12H], and [14H]; [16H] of

the data memory, respectively. Port A is an input port

only while Port B and Port C (PC0 and PC1) are

bidirectional I/O ports. For input operation, the ports A,

B, and C are non-latched, i.e., the inputs have to be

ready at the T2 rising edge of the instruction

²MOV A,

[m]

² (m=12H, 14H, 16H). For output operation, data is

latched and then remains unchanged until the output

latch is rewritten.

8 - s t a g e P r o g r a m m a b l e

. r e q u e n c y D i v i d e r

[ 7 : 0 ]

S y s t e m C l o c k

D u t y c o n t r o l l e r

B Z

A d d r e s s 1 D H D a t a B u s [ 7 : 0 ]

S P . 1 0

S P . 1 1

D i v i d e d b y 1 ,

2 , 4 , 8 O p t i o n

3 2 . 7 6 8 k H z

S P . 1 7

S P . 1 7 : 0

S P . 1 7 : 1

B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0

1 / 2 d u t y

1 / 4 d u t y

S P . 1 8

Programmable tone generator

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