Pin Assignment

Pin Description

Pin Name

I/O

Internal

Connection

Description

VP

I

Operational

Amplifier

Operational amplifier non-inverting input

VN

I

Operational amplifier inverting input

GS

O

Operational amplifier output terminal

VREEF

O

VREF

X1

I

oscillator

The system oscillator consists of an inverter, a bias resistor and the necessary

load capacitor on chip.

A standard 3.579545MHz crystal connected to X1 and X2 terminals imple-

ments the oscillator function.

X2

O

PWDN

I

CMOS IN

Pull-low

Active high. This enables the device to go into power down mode and inhibits

the oscillator. This pin input is internally pulled down.

INH

I

CMOS IN

Pull-low

Logic high. This inhibits the detection of tones representing characters A, B, C

and D. This pin input is internally pulled down.

VSS

¾¾

Negative power supply, ground

OE

I

CMOS IN

Pull-high

D0~D3 output enable, high active

D0~D3

O

CMOS OUT

Tristate

Receiving data output terminals

OE=

²H²: Output enable

OE=

²L²: High impedance

DV

O

CMOS OUT

Data valid output

When the chip receives a valid tone (DTMF) signal, the DV goes high; other-

wise it remains low.

EST

O

CMOS OUT

Early steering output (see Functional Description)

RT/GT

I/O

CMOS IN/OUT

Tone acquisition time and release time can be set through connection with ex-

ternal resistor and capacitor.

VDD

¾¾

Positive power supply, 2.5V~5.5V for normal operation

HT9170B/HT9170D

Rev. 1.10

2

September 24, 2002

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

1

2

3

4

5

6

7

8

9

V D D

R T / G T

E S T

D V

D 3

D 2

D 1

D 0

O E

V P

V N

G S

V R E .

I N H

P W D N

X 1

X 2

V S S

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

1

2

3

4

5

6

7

8

9

V D D

R T / G T

E S T

D V

D 3

D 2

D 1

D 0

O E

V P

V N

G S

V R E .

I N H

P W D N

X 1

X 2

V S S

H T 9 1 7 0 B

1 8 D I P - A

H T 9 1 7 0 D

1 8 S O P - A