HT1647

Rev. 1.30

11

November 10, 2005

Bias Generator

The HT1647 bias voltage belongs to internal resistor

type. It provides two kinds of bias option named 1/5 bias

and 1/4 bias respectively. It is recommended to select

1/5 bias to fit TN-type, STN-type LCDs and select 1/4

bias to fit ECB-type LCDs. It also provides three kinds of

bias current option by programming to suitably drive an

LCD panel. The three kinds of bias current are large,

middle, and small, respectively. Usually, large panel

LCD can be excellently displayed by large bias current.

Relatively, it consumes large current when LCD ON

command is used. Small bias current provides low

power consumption during On condition when the LCD

is normally displayed. The following are the reference

value table.

Bias

Large Bias Current

Middle Bias Current

Small Bias Current

4V

1/5

300

mA

100

mA40mA

4V

1/4

375

mA

125

mA50mA

V R

*

*

R

V S S

V 2

V 3

V 4

V 1

1 / 5 b i a s

R

V S S

V 2

V 3

V 4

V 1

1 / 4 b i a s

R

R

R

R

R

R

R

R

V D D

V L C D

V D D

V L C D

* T h e v o l t a g e a p p l i e d t o V L C D p i n m u s t b e l o w e r t h a n V D D

*

V R

*

Internal Resistor Type Bias Generator Configurations

Interfacing

Only six lines are required to interface with the HT1647.

The CS line is used to initialize the serial interface circuit

and to terminate the communication between the host

controller and the HT1647. If the CS pin is set to 1, the

data and command issued between the host controller

and the HT1647 are first disabled and then initialized.

Before issuing a mode command or mode switching, a

high level pulse is required to initialize the serial inter-

face of the HT1647. The DB0~DB3 are the 4-bit parallel

data input/output lines. Data to be read or written or

commands to be written have to pass through the

DB0~DB3 lines. The RD line is the READ clock input.

Data in the RAM are clocked out on the falling edge of the

RD signal, and the clocked out data will then appear on

the DB0~DB3 lines. It is recommended that the host

controller read correct data during the interval between

the rising edge and the next falling edge of the RD signal.

The WR line is the WRITE clock input. The data, ad-

dress, and command on the DB0~DB3 lines are all

clocked into the HT1647 on the rising edge of the WR

signal. There is an optional IRQ line to be used as an in-

terface between the host controller and the HT1647.

The IRQ pin can be selected as a timer output or a WDT

overflow flag output by the S/W setting. The host con-

troller can perform the time base or the WDT function by

connecting with the IRQ pin of the HT1647.