Pad Coordinates

Unit: mil

Pad No.

X

Y

Pad No.

X

Y

1

-68.43

71.78

28

48.15

-71.91

2

-68.43

59.46

29

54.78

-71.91

3

-68.43

52.83

30

69.32

-10.67

4

-69.19

39.14

31

69.32

-4.04

5

-69.36

23.89

32

69.32

2.59

6

-69.36

16.32

33

69.32

9.22

7

-69.36

9.69

34

69.32

15.85

8

-69.36

3.06

35

69.32

22.48

9

-69.36

-3.57

36

69.32

29.11

10

-69.36

-16.92

37

69.32

35.74

11

-69.36

-33.83

38

69.32

42.37

12

-69.36

-43.52

39

69.32

49.00

13

-69.36

-50.15

40

69.32

55.63

14

-69.36

-56.78

41

69.32

62.26

15

-69.36

-63.41

42

69.32

68.89

16

-69.36

-70.04

43

14.19

71.78

17

-39.23

-71.14

44

7.57

71.78

18

-32.60

-71.14

45

0.94

71.78

19

-20.19

-71.14

46

-5.70

71.78

20

-13.56

-71.14

47

-12.32

71.78

21

-1.15

-71.14

48

-18.95

71.78

22

5.48

-71.14

49

-25.58

71.78

23

15.00

-71.91

50

-32.22

71.78

24

21.63

-71.91

51

-38.85

71.78

25

28.26

-71.91

52

-45.47

71.78

26

34.89

-71.91

53

-52.10

71.78

27

41.52

-71.91

54

-58.74

71.78

Pad Description

Pad No.

Pad Name

I/O

Description

1CS

I

Chip selection input with Pull-high resistor. When the CS is logic high, the

data and command read from or written to the HT1622 are disabled. The se-

rial interface circuit is also reset. But if CS is at logic low level and is input to

the CS pad, the data and command transmission between the host controller

and the HT1622 are all enabled.

2RD

I

READ clock input with Pull-high resistor. Data in the RAM of the HT1622 are

clocked out on the falling edge of the RD signal. The clocked out data will ap-

pear on the data line. The host controller can use the next rising edge to latch

the clocked out data.

3WR

I

WRITE clock input with Pull-high resistor. Data on the DATA line are latched

into the HT1622 on the rising edge of the WR signal.

4

DATA

I/O

Serial data input or output with Pull-high resistor

5

VSS

¾

Negative power supply, ground

6

OSCI

I

If the system clock comes from an external clock source, the external clock

source should be connected to the OSCI pad.

7

VDD

¾

Positive power supply

8

VLCD

I

LCD operating voltage input pad

9

IRQ

O

Time base or Watchdog Timer overflow flag, NMOS open drain output

10, 11

BZ, BZ

O

2kHz or 4kHz tone frequency output pair

12~14

T1~T3

I

Not connected

15~22

COM0~COM7

O

LCD common outputs

23~54

SEG0~SEG31

O

LCD segment outputs

HT1622

Rev. 1.40

3

February 6, 2007