HT86R384 datasheet(17/41 Pages) HOLTEK

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HT86R384

Rev. 0.10

May 18, 2007

Preliminary

The TMR0C is the Timer/Event Counter 0 control regis-

ter, which defines the Timer/Event Counter 0 options.

The Timer/Event Counter 1 has the same options as the

Timer/Event Counter 0 and is defined by TMR1C.

The timer/event counter control registers define the oper-

ating mode, counting enable or disable and active edge.

The TM0, TM1 bits define the operating mode. The

event count mode is used to count external events,

which implies that the clock source comes from an ex-

ternal (TMR0/TMR1 is connected to PC4/PC5) pin. The

timer mode functions as a normal timer with the clock

source coming from the instruction clock. The pulse

width measurement mode can be used to count the high

or low level duration of an external signal

(TMR0/TMR1). The counting method is based on the in-

struction clock.

In the event count or timer mode, once the timer/event

counter starts counting, it will count from the current

contents in the timer/event counter to FFFFH. Once an

overflow occurs, the counter is reloaded from the

timer/event counter preload register and generates a

corresponding interrupt request flag (T0F/T1F; bit 5/6 of

INTC) at the same time.

In the pulse width measurement mode with the TON and

TE bits equal to one, once the TMR0/TMR1 has re-

ceived a transient from low to high (or high to low; if the

TE bit is 0) it will start counting until the TMR0/TMR1 re-

turns to the original level and resets TON. The mea-

sured result will remain in the timer/event counter even if

the activated transient occurs again. In other words,

only one cycle measurement can be done. When TON

is set again, the cycle measurement will function again

as long as it receives further transient pulses. Note that,

in this operating mode, the timer/event counter starts

counting not according to the logic level but according to

the transient edges. In the case of counter overflows,

the counter is reloaded from the timer/event counter

preload register and issues the interrupt request just like

in the other two modes.

To enable the counting operation, the Timer ON bit

(TON; bit 4 of TMR0C/TMR1C) should be set to 1. In the

pulse width measurement mode, TON will be cleared

automatically after the measurement cycle is complete.

But in the other two modes TON can only be reset by in-

struction. The overflow of the timer/event counter is one

of the wake-up sources. No matter what the operation

mode is, writinga0to ET0I/ET1I can disable the corre-

sponding interrupt service.

In the case of a Timer/Event Counter OFF condition,

writing data to the timer/event counter preload register

will also reload that data to the timer/event counter. But

if the timer/event counter is turned on, data written to the

timer/event counter will only be kept in the timer/event

counter preload register. The timer/event counter will

continue to operate until an overflow occurs.

When the Timer/Event Counter (reading TMR0H/

TMR1H) is read, the clock will be blocked to avoid er-

rors. As this may result in a counting error, this must be

taken into consideration by the programmer.

Bit No.

Label

Function

0~2, 5

Unused bit, read as

²0²

3TE

To define the TMR0/TMR1 active edge of Timer/Event Counter

(0=active on low to high; 1=active on high to low)

TON

To enable/disable timer counting (0=disabled; 1=enabled)

TM0,

TM1

To define the operating mode (TMR1, TMR0)

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

TMR0C (0EH)/TMR1C (11H) Register

Bit No.

Label

Function

0~2, 5

Unused bit, read as

²0²

3TE

To define the TMR0/TMR1 active edge of Timer/Event Counter

(0=active on low to high; 1=active on high to low)

TON

To enable/disable timer counting (0=disabled; 1=enabled)

TM0,

TM1

To define the operating mode (TMR1, TMR0)

01=Unused

10=Timer mode (internal clock)

11=Unused

00=Unused

TMR2C (22H) Register

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