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SC339 датащи(PDF) 11 Page - Semtech Corporation

номер детали SC339
подробное описание детали  Ultra Low Output Voltage Linear FET Controller
PDF  15 Pages
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производитель  SEMTECH [Semtech Corporation]
домашняя страница  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

SC339 датащи(HTML) 11 Page - Semtech Corporation

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© 2006 Semtech Corp.
www.semtech.com
SC339
POWER MANAGEMENT
Applications Information (Cont.)
Now,
We choose C3 = 470nF as the standard value.
Soft-Start Behavior
Atstart-up,V
OUT first ramps linearly from ground at the rate of
~0.5V/ms (+/- 25%) for about 800us. The linear ramping is
followedbyaphaseofsmoothsettlingforabout700usatthe
end of which the output has fully settled (to better than 1%).
The total start-up time of about 1.5ms is kept within 1ms
- 2ms window, and this is regardless of the loading and
of the external components connected to the device.
SC339 Start-Up Response
C3 = ½ • • R3 • 3kHz = 530nF
Layout Guidelines
The advantages of using the SC339 to drive external
MOSFETs are:
a) that the bandgap reference and control circuitry are in a
die that does not contain high power dissipating devices
and,
b) that the device itself does not need to be located right
next to the power devices. Thus very accurate output
voltages can be obtained since changes due to heating
effects will be minimal.
The 0.1μF bypass capacitor should be located close to the
supply (IN) and GND pins, and connected directly to the
ground plane.
The feedback resistors should be located at the device,
with the sense line from the output routed from the load
(or top end of the droop resistor if passive droop is being
used) directly to the feedback chain. If passive droop is
being used, the droop resistor should be located next to the
load to avoid adding additional unplanned droop. Sense
and drive lines should be routed away from noisy traces
or components.
For very low input to output voltage differentials, the
input to output/load path should be as wide and short
as possible. Where greater headroom is available, wide
traces may suffice.
Power dissipation within the device is practically
negligible, thus requiring no special consideration dur-
ing layout. The MOSFET pass devices should be laid out
according to the manufacturer’s guidelines for the power
being dissipated within them.



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