SC411 datasheet(11/27 Pages) SEMTECH

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SC411

POWER MANAGEMENT

Application Information (Cont.)

The current limit circuitry also protects against negative

over-current (i.e. when the current is ﬂowing from the load

to PGND through the inductor and bottom MOSFET). In

this case, when the bottom MOSFET is turned on, the

phase node, LX, will be higher than PGND initially. The

SC411 monitors the voltage at LX, and if it is greater than

a set threshold voltage of 125mV (nom) the bottom MOS-

FET is turned off. The device then waits for approximately

2.5μs and then DL goes high for 300ns (typ) once more

to sense the current. This repeats until either the over-

current condition goes away or the part latches off due to

output over-voltage (see Output Over-voltage Protection).

Power Good Output

The power good output is an open-drain output and re-

quires a pull-up resistor. When the output voltage is 16%

above or 10% below its set voltage, PGD gets pulled low. It

is held low until the output voltage returns to within these

tolerances once more. PGD is also held low during start-

up and will not be allowed to transition high until soft start

is over (440 switching cycles) and the output reaches 90%

of its set voltage. There is a 5μs delay built into the PGD

circuitry to prevent false transitions.

Output Over-Voltage Protection

When the output exceeds 16% of the its set voltage the

low-side MOSFET is latched on. It stays latched on and

the controller is latched off until reset*. There is a 5μs

delay built into the OV protection circuit to prevent false

transitions.

Output Under-Voltage Protection

When the output is 30% below its set voltage the output

is latched in a tri-stated condition. It stays latched and

the controller is latched off until reset*. There is a 5μs

delay built into the UV protection circuit to prevent false

transitions.

POR, UVLO and Soft-Start

An internal power-on reset (POR) occurs when VCCA ex-

ceeds 3V, starting up the internal biasing. VCCA under-

voltage lockout (UVLO) circuitry inhibits the controller until

VCCA rises above 4.2V. At this time the UVLO circuitry

resets the fault latch and soft-start counter, and allows

switching to occur if the device is enabled. Switching al-

ways starts with DL to charge up the BST capacitor. With

the soft-start circuit (automatically) enabled, it will pro-

gressively limit the output current (by limiting the current

out of the ILIM pin) over a predetermined time period of

440 switching cycles.

The ramp occurs in four steps:

1) 110 cycles at 25% ILIM with double minimum off-time

(for purposes of the on-time one-shot, there is an internal

positive offset of 120mV to VOUT during this period to aid

in startup).

2) 110 cycles at 50% ILIM with normal minimum off-

time.

3) 110 cycles at 75% ILIM with normal minimum off-time.

4) 110 cycles at 100% ILIM with normal minimum off-

time.

At this point the output under-voltage and power good cir-

cuitry is enabled.

There is 100mV of hysteresis built into the UVLO circuit

and when VCCA falls to 4.1V (nom) the output drivers are

shut down and tri-stated.

MOSFET Gate Drivers

The DH and DL drivers are optimized for driving moder-

ate-sized high-side, and larger low-side power MOSFETs.

An adaptive dead-time circuit monitors the DL output and

prevents the high-side MOSFET from turning on until DL is

fully off (below ~1V). Semtech’s SmartDriverTM FET drive

ﬁrst pulls DH high with a pull-up resistance of 10Ω (typ)

until LX = 1.5V (typ). At this point, an additional pull-up

device is activated, reducing the resistance to 2Ω (typ);

This negates the need for an external gate or boost re-

sistor. The adaptive dead time circuit also monitors the

phase node, LX, to determine the state of the high side

MOSFET, and prevents the low side MOSFET from turning

on until DH is fully off (LX below ~1V). Be sure there is

low resistance and low inductance between the DH and

DL outputs to the gate of each MOSFET.

* Note: to reset from any fault, VCCA or EN/PSV must be toggled.

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