HT83R074 datasheet(13/38 Pages) HOLTEK

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HT83R074

Rev. 1.00

May 17, 2007

WS7

WS6

WS5

WS4

WS3

WS2

WS1

WS0

Division Ratio

¾¾¾¾¾

000

1:1

¾¾¾¾¾

001

1:2

¾¾¾¾¾

010

1:4

¾¾¾¾¾

011

1:8

¾¾¾¾¾

1:16

¾¾¾¾¾

1:32

¾¾¾¾¾

1:64

¾¾¾¾¾

1:128

WDTS (09H) Register

Interrupt Source

Priority

Vector

Time Base Interrupt

04H

Timer Counter 0 Overflow

08H

Timer Counter 1 Overflow

0CH

Oscillator Configuration

The HT83R074 provides two oscillator circuits for sys-

tem clock, i.e., RC oscillator and Crystal oscillator. No

matter what type of oscillator.. The signal is used for the

system clock. The HALT mode stops the system oscilla-

tor to conserve power. If the RC oscillator is used, an ex-

ternal resistor between OSC1 and VSS is required, and

the range of the resistance should be from 144k

W to

275k

W. The system clock, divided by 4. The RC oscilla-

tor provides the most cost effective solution. However,

the frequency of the oscillation may vary with VDD, tem-

perature, and the chip itself due to process variations. It

is therefore not suitable for timing sensitive operations

where accurate oscillator frequency is desired.

On the other hand, if the crystal oscillator is selected, a

crystal across OSC1 and OSC2 is needed to provide the

feedback and phase shift required for the oscillator, and

no other external components are required. A resonator

may be connected between OSC1 and OSC2 to replace

the crystal and to get a frequency reference, but two ex-

ternal capacitors in OSC1 and OSC2 are required.

Watchdog Timer

- WDT

The WDT clock source is implemented by a dedicated

RC oscillator (WDT oscillator) or instruction clock (sys-

tem clock divided by 4), decided by options. This timer is

designed to prevent a software malfunction or sequence

jumping to an unknown location with unpredictable re-

sults. The Watchdog Timer can be disabled by option. If

the Watchdog Timer is disabled, all the executions re-

lated to the WDT result in no operation.

Once the internal WDT oscillator (RC oscillator with pe-

riod 78

ms normally) is selected, it is first divided by 256

(8-stages) to get the nominal time-out period of approxi-

mately 20ms. This time-out period may vary with tem-

perature, VDD and process variations. By invoking the

WDT prescaler, longer time-out period can be realized.

Writing data to WS2, WS1, WS0 (bit 2,1,0 of

WDTS(09H)) can give different time-out period.

If WS2, WS1, WS0 all equal to 1, the division ratio is up to

1:128, and the maximum time-out period is 2.6 seconds.

If the device operates in a noisy environment, using the

on-chip RC oscillator (WDT OSC) is strongly recom-

mended, since the HALT will stop the system clock.

The WDT overflow under normal operation will initialize

²chip reset² and set the status bit ²TO². Whereas in

the HALT mode, the overflow will initialize a

²warm re -

set

² only the Program Counter and SP are reset to zero.

To clear the contents of the WDT (including the WDT

prescaler), three methods are adopted; external reset

(external reset (a low level to RES), software instruc-

tions, or a

²HALT² instruction. The software instruction

²CLR WDT² and execution of the ²CLR WDT² instruc-

tion will clear the WDT.

C r y s t a l O s c i l l a t o r

R C O s c i l l a t o r

O S C 1

O S C 2

f S Y S / 4

O S C 1

V D D

System Oscillator

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