SC488MLTRT datasheet(17/24 Pages) SEMTECH

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SC488

POWER MANAGEMENT

Application Information (Cont.)

Finally, we calculate the current limit resistor value. As de-

scribed in the current limit section, the current limit looks

at the “valley current”, which is the average output cur-

rent minus half the ripple current.

)

MIN

(

RIPPLE_VBA

OUT

VALLEY

The ripple at low battery voltage is used because we want

to make sure that current limit does not occur under nor-

mal operating conditions.

Ohms

1.4

(ON)

1.2

VALLEY

ILIM

For our example:

VALLEY = 8.31A, RDS(ON) = 4mΩ, giving RILIM = 5.62kΩ

Thermal Considerations

The junction temperature of the device may be calculated

as follows:

J = TAMB + θJA

where T

J is the junction temperature, TAMB is the ambient

temperature, PD is the total SC488 device dissipation. The

SC488 device dissipation can be determined using:

PD = VCCA • ICCA + VDDP • IDDP + VTT • |ITT|

The ﬁ rst two terms are losses for the analog and gate drive

circuits and generally do not present a thermal problem.

Typical ICCA (VCCA operating current) is roughly 1.5mA,

which creates 7.5mW loss from the 5V VCCA supply. The

VDDP supply current is used to drive the MOSFETs and

can be much higher, on the order of 30mA, which can

create up to 150mW of dissipation.

The last term, VTT * |ITT|, is the most signiﬁ cant term

from a thermal standpoint. The VTT regulator is a linear

device and will dissipate power proportional to the VTT

current and the voltage drop across the regulator. If VTT

= VDDQ/2, then the voltage drop across the regulator

is always VDDQ2, regardless of whether the regulator is

sinking or sourcing current. In either case the power lost in

the VTT regulator is VTT * |ITT|. The average or long-term

value for ITT should be used. The thermal resistance of the

MLPQ package is affected by PCB layout and the available

ground planes and vias which conduct heat away. A typical

value is 29°C/watt.

Example:

ICCA = 1.5mA

IDDP = 25mA

VCCA = VDDP = 5V

VTT = 1.25V

ITT = 0.75A (average)

Ambient = 45 degrees C

Thermal resistance = 29

D = 5V • 0.0015 A + 5V • 0.025A + 0.9V • |0.75|A

PD = 0.808W

J = TAMB + PD • TJA = 45 + 0.808W • 29°C/W = 68.4°C

Layout Guidelines

One (or more) ground planes are recommended to

minimize the effect of switching noise and copper losses,

and maximize heat dissipation. The IC ground reference,

VSSA, should be connected to PGND1 and PGND2 as a

star connection at the thermal pad, which in connects

using 4 vias to the ground plane. All components that are

referenced to VSSA should connect to it directly on the chip

side, and not through the ground plane.

VDDQ: The feedback trace must be kept far away from

noise sources such as switching nodes, inductors and

gate drives. Route the feedback trace in a quiet layer if

possible, from the output capacitor back to the chip. Chip

supply decoupling capacitors (VCCA, VDDP) should be

located next to the pins (VCCA/VSSA, VDDP/PGND1) and

connected directly to them on the same side.

VTT: Because of the high bandwidth of the VTT regulator,

proper component placement and routing is essential to

prevent unwanted high-frequency oscillations which can

be caused by parasitic inductance and noise. The input

capacitors should be located at the VTT input pins (VTTIN

and PGND2), as close as possible to the chip to minimize

parasitics. Output capacitors should be directly located at

the VTT output pins (VTT and PGND2). The routing of the

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